Abstract: An embodiment of the present invention discloses a system and method for decoding multiple independent encoded audio streams using a single decoder. The system includes one or more parsers, a preprocessor, an audio decoder, and a renderer. The parser extracts individual audio frames from each input audio stream. The preprocessor combines the outputs of all parsers into a single audio frame stream and enables sharing of the audio decoder among multiple independent encoded audio streams. The audio decoder decodes the single audio frame stream and provides a single decoded audio stream. And the renderer renders the individual reconstructed audio streams from the single decoded audio stream.

Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b?1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.

Abstract: An apparatus for measuring time interval between two selected edges of a clock signal. includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first constant incremental delay at each tap to the first edge. Second multi-tap delay module provides a second constant incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has a first input terminal and a second input terminal. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.

Abstract: Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced.

Abstract: A single-ended bit line based storage system. The storage system includes a first set of storage cells, a second set of storage cells, a first set of reference storage cells, a second set of reference storage cells, and a differential sensing block. The memory core is split vertically in half vertically to form the first set of storage cells and the second set of storage cells. The first set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The second set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The differential sensing block is coupled to the first set of storage cells and the second set of storage cells for generating an output data signal on receiving a control signal.

Abstract: A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.

Abstract: A memory device includes bitlines, wordlines and a matrix of memory cells arranged in rows and columns. Each of the bitlines is electrically connected to memory cells in one of the columns. Each of the wordlines is electrically connected to memory cells in one of the rows. A bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.

Abstract: A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input receives a reference voltage provided by a corresponding single bit-line memory cell from a complementary memory bank. A supporting voltage is added-to/subtracted-from the reference voltage by providing a “bump” or “dip” mechanism or by utilizing a charge-sharing structure, in order to compensate for the variation in the sensed bit-line voltage over the duration of the sensing interval as well as for the disparity in voltage level from cell to cell.

Abstract: A memory interface module provides interfacing between a host processor with multiple flash memories and parallel interfaces of varying protocols. The interface module includes multiple register files, multiple operation information registers, an internal memory, a flash interface portion, and a finite state machine (FSM). The register files receive a command from the host processor for controlling an operation of multiple flash memories. The operation information registers execute and store the command and operation information. The internal memory receives and stores host data from the host processor. The internal memory further stores flash data extracted from multiple flash memories. The flash interface portion interacts with the memory devices connected to the controller. The FSM extracts the command and the operation information from the register files, which are programmed by the user and controls the control signals of the memory devices connected to the controller through the flash interface.

Abstract: A novel method for introducing delays in self timed memories is disclosed. In the proposed method, delays are introduced by introducing a capacitance on the path of signal to be delayed. The capacitances are realized by using idle lying metal layers in the circuit. The signal to be delayed is connected to these idle lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since, in the proposed method, idle-lying metal capacitances are utilized, the circuit can be implemented using minimum amount of additional hardware. Also delay provided by the proposed circuitry is a function of memory cell spice characteristics and core parasitic capacitances.

Abstract: Electromigration may cause a fault to appear in an integrated circuit located on a semiconductor chip. To detect such a fault, at least one resistive test structure is provided separated from the integrated circuit and located on at least one metallization level of the integrated circuit. During operation of the integrated circuit, the resistive test structure is sensed. Detection of a voltage difference between two points of the resistive test structure is indicative of a fault.

Abstract: A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell.

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract: Memory devices and methods of operating a memory cell are disclosed in which a bitline can be grounded after charge sharing with an electrically floating ground line and before writing data to the memory cell. An electric potential of an upper power supply node of a memory cell can be lowered and an electric potential of a lower power supply node of the memory cell can be raised before writing data to the memory cell.

Abstract: A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.

Abstract: An image processing arrangement includes an input to receive an indicator of a power characteristic related to an image processing arrangement and an image processor to process an image based on the indicator of the power characteristic.

Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.

Abstract: A level shifter includes an output stage transistor and a level controller. The level controller receives a selection signal and provides a reference voltage at a gate terminal of the output stage transistor based on the selection signal. The output stage transistor, on being enabled by the reference voltage, provides a first level shifted output based on a first output reference voltage.

Abstract: A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased.