Abstract: A comparator has a hysteresis value which is adjustable in response to a hysteresis setting control signal. An input of the comparator receives a modulated signal contaminated by in-band noise. A pulsed signal output from the comparator is converted by a digital to analog converter circuit an analog signal. That analog signal is converted by an analog to digital converter to a digital signal value. A comparison circuit compares the digital signal value to a threshold value and generates the hysteresis setting control signal to adjust the hysteresis value of the comparator in response to a result of the comparison in order to suppress the in-band noise from the output of the pulsed signal output from the comparator.

Abstract: An electronic chip includes a memory circuit including: a semiconductor substrate having selection transistors arranged therein and an interconnection stack arranged on the semiconductor substrate. The interconnection stack includes a succession of levels, each level including a first insulating layer and a second insulating layer having interconnection elements defined therein. The memory circuit includes a plurality of memory cells arranged above the interconnection stack. Each memory cell is adapted to be electrically coupled to a selection transistor via a first conductive via running through the entire thickness of the interconnection stack.

Abstract: Provided is a power electronic circuit comprising at least one power transistor the gate of which is coupled to a control circuit, and the source of which is coupled to a first contact pad, wherein the control circuit is coupled to a second contact pad, and wherein the first and second contact pads are configured to be decoupled from each other when the power electronic circuit is in a configuration for stress testing the gate of the power transistor, and configured to be coupled to each other when the power transistor and control circuit are encapsulated.

Abstract: The present disclosure is directed to a device and method for human fall detection solution. Fall detection is performed by a low power inertial measurement unit (IM U) that is communicatively coupled between a pressure sensor and an application processor. The IM U includes one or more motions sensors, such as an accelerometer and gyroscope. The application processor is the main processor of the containing device. The IM U receives pressure sensor data from the pressure sensor, and executes the fall detection using both the pressure sensor data and accelerometer data.

Abstract: A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pattern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.

Abstract: The present description concerns a circuit for converting from a first alternating voltage to a second voltage. The circuit includes: a first thyristor; a first control circuit of the first thyristor; a power factor correction circuit comprising a coil; and a first circuit configured to convert a third voltage into a fourth DC voltage. The third voltage corresponds to a difference between a potential at a first node connected to an output node of the coil and a reference potential. The fourth DC voltage is configured to supply the first control circuit of the first thyristor, and is referenced with respect to the same reference potential as the third voltage.

Abstract: An HS switching transistor is coupled between a high-side node and a switching node. An LS switching transistor is coupled between the switching node and a low-side node. An inductive load is coupled to the switching node in a way where one of the HS/LS switching transistors is freewheeling. In response to detection of a short circuit occurring at the switching node with the freewheeling switching transistor in the conductive state: an electrical signal at the switching node is sensed, a comparison is made between the sensed electrical signal and a threshold level, and a driving signal is provided to control freewheeling switching transistor to switch to the non-conductive state when the comparison indicates that the electrical signal has reached the threshold level.

Abstract: A semiconductor device includes a semiconductor body; a gate; a field plate, spaced from the gate, the field plate having a strip-like shape with main extensions along a first direction, the strip-like shape having a first and a second end opposite to one; a first conductive pad in electrical contact with the field plate at the first end through a first connecting region; a second conductive pad in electrical contact with the field plate at the second end through a second connecting region; and a third conductive pad in electrical contact with the field plate at the second end through a third connecting region. The conductive pads allow the use of the field plate as a temperature sensor.

Abstract: A piezoelectric actuator-system includes an inductor and driver-circuit having switches for transferring energy between first and second actuators and the inductor, and between a voltage-supply node and the inductor. Control circuitry determines whether a next phase in which to operate the driver-circuit is a charging-phase or a recovery-phase. Either the charging-phase or recovery-phase may include, after a freewheeling sub-phase, a pre-charge sub-phase to place a given one of the switches connected to the first actuator near a zero-voltage switching condition. Either the charging-phase or recovery-phase may include, after a sub-phase in which a parasitic capacitance is charged, an additional recovery sub-phase in which the charge from the parasitic capacitance is recovered to the voltage-supply node.

Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor device includes forming a first front layer and a first rear layer of a first material respectively on a front main face and a rear main face of a semiconductor substrate wafer; forming a first plurality of trenches and a second plurality of trenches respectively in a surface of the first front layer and in a surface of the first rear layer; forming a second front layer of a second material on the first front layer, where the second front layer extends over the first front layer, in the first plurality of trenches, and between the first plurality of trenches on the surface of the first front layer; and forming a second rear layer of the second material on the surface of the first rear layer, wherein the second rear layer extends over the first rear layer, in the second plurality of trenches, and between the second plurality of trenches on the surface of the first rear layer.

Abstract: The present disclosure concerns a photodiode including at least one memory area, each memory area including at least two charge storage regions.

Abstract: A DC-DC boost converter includes an input receiving an input voltage and an output producing an output voltage. A switching stage is formed by a low-side transistor arranged between a switching node and a ground node, and a high-side transistor arranged between the switching node and the output. The high-side transistor includes a body diode having an anode coupled to the switching node and a cathode coupled to the output. The converter is controlled in an asynchronous operation mode where the low-side transistor is driven alternately to a conductive state and a non-conductive state, and the high-side transistor is driven steadily to a non-conductive state. A variable load circuit is selectively coupled between the two output terminals when the converter is in the asynchronous operation mode in order to sink a load current having a value that is a function of a value of the input voltage.

Abstract: An integrated circuit package includes a substrate having a first surface and a second surface. An electronic integrated circuit chip has a first surface and a second surface, with the second surface mounted on the first surface of the substrate. A preformed glass cover is assembled on the first surface of the substrate and arranged to contain the electronic integrated circuit chip.

Abstract: A laminated structure includes metal tracks. In a method for making, a first layer of a first dielectric material is deposited on a substrate. One or more openings are then made in the first layer. A second dielectric material is then deposited within the openings formed in the first layer. The second dielectric material has dielectric properties distinct from the dielectric properties of the first dielectric material.

Abstract: The present disclosure is directed to devices and methods for performing context recognition. The context recognition detects whether the device is in a lid closed mode or a tablet mode. The context recognition is configured to handle exception cases including a first exception case in which context recognition is started while in an upright mode, and a second exception case in which context recognition is started while the device is in a lid closed mode or a tablet mode.

Abstract: The disclosure concerns an electronic device provided with two high electron mobility transistors stacked on each other and having in common their source, drain, and gate electrodes. For example, each of these electrodes extends perpendicularly to the two transistors. For example, the source and drain electrodes electrically contact the conduction channels of each of the transistors so that said channels are electrically connected in parallel.

Abstract: A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.

Abstract: An electronic system is configured to generate a sequential logic signal. The electronic system includes a first ring oscillator including a first plurality of cascaded inverter stages. A combinational logic circuit is configured to generate the sequential logic signal by combining signals at the output terminals of at least two of the inverter stages of the first ring oscillator. The electronic system further includes a second ring oscillator including a second plurality of cascaded inverter stages. A bias current source is configured to supply the inverter stages of the second ring oscillator with a bias current, and a first voltage is generated at the inverter stages of the second ring oscillator. A voltage follower is configured to supply the inverter stages of the first ring oscillator with a second voltage corresponding to the first voltage generated at the inverter stages of the second ring oscillator.

Abstract: According to an embodiment, a method includes adjusting a reference generator into a first configuration based on a temporary trim value resulting, in a first reference voltage and a first reference current being generated for a first memory. The method further includes performing an integrity check on an initial set of data downloaded from the first memory based on the first reference voltage and the first reference current. The initial set of data includes a first trim value. The method further includes downloading contents from the first memory into a second memory in response to a successful integrity check after adjusting the reference generator into a second configuration. In the second configuration, the reference generator generates a second reference voltage and a second reference current for the first memory. The reference generator is adjusted by the first trim value in response to a successful integrity check.

Abstract: According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.