Patents Assigned to STMicroelectronics (Research& Development)
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Patent number: 12340014Abstract: According to an embodiment, a method for determining an orientation of an object in a field-of-view of a time-of-flight sensor is proposed. The method includes receiving a sensor readout from the time-of-flight sensor; feeding the sensor readout as an input to a neural network, the neural network trained on a set of data with a binary output that classifies the input as being valid or invalid based on the orientation of the object with respect to the time-of-flight sensor; rotating the sensor readout for a set number of rotations and feeding each rotation as an input to the neural network to determine a valid orientation of the object; and rotating an image on a display interface based on the rotation corresponding to the valid orientation of the object as determined by the neural network.Type: GrantFiled: February 22, 2024Date of Patent: June 24, 2025Assignee: STMicroelectronics International N.V.Inventor: Carl Erik Larsen
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Patent number: 12340824Abstract: In accordance with an embodiment, a circuit is configured to vary an intensity of a drive current of a resistive heater element based on the digital control signal. The circuit includes and output circuit configured to control a respective slew rate and an electric energy dissipated in the resistive heater element independently of a resistance value of the resistive heater element.Type: GrantFiled: February 5, 2024Date of Patent: June 24, 2025Assignee: STMicroelectronics S.r.l.Inventors: Marco Mazzini, Marco Ciuffolini, Enrico Mammei, Paolo Pulici
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Patent number: 12342641Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.Type: GrantFiled: June 14, 2024Date of Patent: June 24, 2025Assignees: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SASInventors: Raul Andres Bianchi, Marios Barlas, Alexandre Lopez, Bastien Mamdy, Bruce Rae, Isobel Nicholson
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Publication number: 20250202227Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.Type: ApplicationFiled: February 28, 2025Publication date: June 19, 2025Applicant: STMicroelectronics International N.V.Inventor: Radhakrishnan SITHANANDAM
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Publication number: 20250197198Abstract: A manufacturing process for microelectromechanical devices includes: on a first wafer forming a structural layer and a stop layer; defining a stop pad from the stop layer; forming a first microelectromechanical structure and a second microelectromechanical structure in the structural layer; forming a contact element protruding from a second wafer; sealing, at a first pressure, the first microelectromechanical structure in a first chamber and the second microelectromechanical structure and the stop pad in a second chamber; fluidically coupling the second chamber to an external environment; and sealing the second chamber at a second pressure. Sealing at the first pressure comprises bonding the second wafer to the first wafer so that the contact element rests on the stop pad. Fluidically coupling comprises defining fluidic passages at an interface between the contact element and the stop pad and opening an access hole through the second wafer in communication with the fluidic passages.Type: ApplicationFiled: December 4, 2024Publication date: June 19, 2025Applicant: STMicroelectronics International N.V.Inventors: Giorgio ALLEGATO, Lorenzo CORSO, Matteo GARAVAGLIA, Federico VERCESI, Mikel AZPEITIA URQUIA
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Publication number: 20250197199Abstract: A process for manufacturing microelectromechanical devices includes forming a dielectric layer and a structural layer on a substrate of a first semiconductor wafer and forming a first and a second microelectromechanical device in the structural layer. The first and second microelectromechanical devices are sealed respectively in a first chamber and in a second chamber at a first pressure. The first chamber is fluidically coupled to an external environment through the substrate and sealed at a second pressure different from the first pressure. To fluidically couple the first chamber to the outside, there are formed a stop layer between the dielectric layer and the structural layer and a cavity fluidically coupled to the first chamber in the dielectric layer. A channel is formed by etching the substrate in a position corresponding to the cavity and the stop layer, and the etching of the substrate is ended against the stop layer.Type: ApplicationFiled: December 4, 2024Publication date: June 19, 2025Applicant: STMicroelectronics International N.V.Inventors: Federico VERCESI, Giorgio ALLEGATO, Lorenzo CORSO, Mikel AZPEITIA URQUIA, Matteo GARAVAGLIA
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Publication number: 20250203977Abstract: A process for manufacturing a vertical conduction MOSFET device including a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body, and has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.Type: ApplicationFiled: February 27, 2025Publication date: June 19, 2025Applicant: STMicroelectronics S.r.l.Inventors: Mario Giuseppe SAGGIO, Alessia Maria FRAZZETTO, Edoardo ZANETTI, Alfio GUARNERA
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Patent number: 12334817Abstract: In a multi-level hybrid DC-DC converter with a flying capacitor, a feedback circuit includes a first oscillator and produces a first clock signal with a frequency dependent on an output voltage. A second oscillator produces a second clock signal having a frequency dependent on a reference voltage. A logic circuit switches, as a function of the first and second clock signals, connection of the flying capacitor between one state where the flying capacitor is connected between an input node and a switching node, and another state where the capacitor is connected between the switching node and a ground node. The duty cycle of the first/second clock signal varies so that when the flying capacitor voltage is lower than a target voltage a duration of the one state is increased, and when the flying capacitor voltage is higher than the target voltage a duration of the another state is increased.Type: GrantFiled: April 10, 2023Date of Patent: June 17, 2025Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Bertolini, Alessandro Gasparini, Paolo Melillo, Salvatore Levantino, Massimo Ghioni
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Patent number: 12332782Abstract: A system on chip (SoC) includes a CPU, a main bus, and a plurality of subsystems. The SoC also includes an address remapping module coupled between the CPU and the bus. The address remapping module quickly and efficiently changes any memory addresses that need to be changed with the CPU requests a read or write operation associated with the addresses.Type: GrantFiled: March 22, 2023Date of Patent: June 17, 2025Assignee: STMicroelectronics International N.V.Inventors: Loris Luise, Fabio Giuseppe De Ambroggi
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Patent number: 12336440Abstract: A memory cell is manufactured by: (a) forming a stack comprising a first layer made of a phase change material and a second layer made of a conductive material; (b) forming a mask on the stack covering only the memory cell location; and (c) etching portions of the stack not covered by the first mask. The formation of the mask covering only the memory cell location comprises defining a first mask extending in a row direction for each row of memory cell locations and then patterning the first mask in a column direction for each column of memory cell locations.Type: GrantFiled: May 23, 2022Date of Patent: June 17, 2025Assignee: STMicroelectronics (Crolles 2) SASInventors: Pascal Gouraud, Laurent Favennec
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Patent number: 12334429Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.Type: GrantFiled: March 8, 2023Date of Patent: June 17, 2025Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Abderrezak Marzaki, Arnaud Regnier, Stephan Niel
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Patent number: 12333276Abstract: System, method, and circuitry for generating a linker model for use by a toolchain associated with a programmable computing device. One or more regions in the memory resources available to the programmable computing devices is defined for used by an application executing on the programmable computing device. One or more sections is defined for those regions for use by the application. Resource boundaries are generated for the application based on the defined regions and the defined sections. A user is enabled to modify the defined regions or the defined sections or the generated resource boundaries. A linker model is then generated based on the available memory resources, the defined regions, the defined sections, and the generated resource boundaries. This linker model is then utilized to generate a linker script for the programmable computing device based the linker syntax compatible with a toolchain linker for the programmable computing device.Type: GrantFiled: June 14, 2024Date of Patent: June 17, 2025Assignee: STMicroelectronics FranceInventor: Tarek Bochkati
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Patent number: 12330934Abstract: Disclosed herein is a process flow for forming a MEMS IMU including an accelerometer and a gyroscope each located in a separate sealed cavity maintained at a different pressure. Formation of the MEMS IMU includes the use of a first vHF release to etch a sacrificial layer underneath a structural layer containing the accelerometer and gyroscope and capping the device under formation to set both cavities at a first pressure. The floor of one of the cavities is formed to including a gas permeable layer. Formation further includes forming a chimney underneath the gas permeable layer and then performing a second vHF release to etch through the gas permeable layer and expose the cavity containing the gas permeable layer so that its pressure may be set to be different than that of the other cavity when the chimney is sealed.Type: GrantFiled: December 20, 2022Date of Patent: June 17, 2025Assignee: STMicroelectronics International N.V.Inventors: Federico Vercesi, Andrea Nomellini, Paolo Ferrari
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Patent number: 12335402Abstract: In accordance with an embodiment, a video flow transmission method includes: the generating, by an image sensor, a video flow comprising first and second images; hashing, by the image sensor, a portion of the first image based on a first hashing configuration to generate a first hash value, the first hashing configuration defining first positions of pixels to be hashed; hashing, by the image sensor, a portion of the second image based on a second hashing configuration to generate a second hash value, the second hashing configuration being different from the first configuration and defining second positions of pixels to be hashed; and transmitting, by the image sensor, the first and second images, and the first and second hash values, to a second device.Type: GrantFiled: January 5, 2023Date of Patent: June 17, 2025Assignee: STMicroelectronics (Grenoble 2) SASInventor: Jérôme Pierre René Chossat
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Patent number: 12329530Abstract: A device for monitoring the health state is made in a chip including a semiconductor die integrating an electric potential sensor and a cardiac parameter determination unit. The potential sensor is configured to detect potential variations on the body of a living being and associated with a heart rhythm and to generate a cardiac signal. The cardiac parameter determination unit is configured to receive the cardiac signal and determine cardiac parameters indicative of a health state. In particular, the cardiac parameter determination unit is configured to detect triggering events and to determine features of the cardiac signal in time windows defined by the triggering events. The die also integrates a decision unit, configured to receive the cardiac parameters and generate a health signal based on a comparison with threshold values. The cardiac parameters include heart rate and QRS-complex.Type: GrantFiled: July 21, 2022Date of Patent: June 17, 2025Assignee: STMicroelectronics S.r.l.Inventors: Enrico Rosario Alessi, Marco Leo, Luca Gandolfi, Fabio Passaniti, Marco Castellano
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Patent number: 12334119Abstract: A voice coil motor (VCM) in a hard disk drive is operated in a discontinuous mode with an alternation of on and off times. A drive current to the VCM is facilitated and countered with a variable voltage across the during the on-times and off-times. The intensity of the drive current is controlled as a function of a Back ElectroMotive Force (BEMF) of the VCM. A method includes sampling during the alternation of on-times and off-times first and second values of the voltage across the VCM. The first value is sampled at a first time in response to the end of the off-time. The second value is sampled at a second time in response to the drive current of the VCM zeroing following the supply of drive current to the VCM being countered during the off-time. The BEMF is calculated as a function of first and second values.Type: GrantFiled: May 30, 2024Date of Patent: June 17, 2025Assignee: STMicroelectronics International N.V.Inventor: Michele Boscolo Berto
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Publication number: 20250192022Abstract: A process is provided for manufacturing electronic components with wettable flanks from a substrate in which chips are formed, the chips being separated by cavities, the process including a first step in which an insulating material layer is deposited and then a second step in which a conductive material layer is deposited on the insulating material layer to form wettable flanks. An electronic component with wettable flanks is also provided.Type: ApplicationFiled: November 27, 2024Publication date: June 12, 2025Applicant: STMicroelectronics International N.V.Inventor: Gregoire DELACOURT
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Publication number: 20250190003Abstract: A linear voltage regulator includes a first amplification stage configured to produce an error signal at an intermediate node as a function of a difference between a first reference voltage and a regulated output voltage. An intermediate amplification stage amplifies the error signal to produce an amplified error signal. A driver stage produces a drive signal as a function of the amplified error signal. A pass device is controlled by the drive signal to produce the regulated output voltage. A feedback circuit produces a feedback current as a function of a difference between the drive signal and a second reference voltage. The feedback current is the sourced to the intermediate node.Type: ApplicationFiled: December 4, 2024Publication date: June 12, 2025Applicant: STMicroelectronics International N.V.Inventor: Stephan DREBINGER
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Publication number: 20250194205Abstract: A method of manufacturing an electronic device includes the steps of: forming, on a first side of a solid body of Silicon, a first covering layer of SiO2, forming, on the first covering layer, a second covering layer of SiN, and forming, on the second covering layer, a third covering layer of TEOS; forming a passing opening through the first, second and third covering layers. The method includes forming a trench at the portion of the solid body exposed through the opening; grow a sacrificial layer, of the first oxide, within the trench and performing in the order: selectively etching part of the second covering layer, completely removing the sacrificial layer and the third covering layer in one or more contextual etching steps.Type: ApplicationFiled: December 3, 2024Publication date: June 12, 2025Applicant: STMicroelectronics International N.V.Inventors: Mario Francesco PISTONI, Simone Dario MARIANI, Paola ZULIANI, Emilie PREVOST, Ambra PISANU
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Publication number: 20250194439Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.Type: ApplicationFiled: February 19, 2025Publication date: June 12, 2025Applicant: STMicroelectronics (Rousset) SASInventor: Philippe BOIVIN