Abstract: In an embodiment, a voltage multiplier comprises an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered sub-sequences. Capacitors are coupled: between each odd intermediate node in the first sub-sequence and the first control node; between each even intermediate node in the first sub-sequence and the second control node; between each odd intermediate node in the second sub-sequence and a corresponding odd intermediate node in the first sub-sequence; and between each even intermediate node in the second sub-sequence and a corresponding even intermediate node in the first sub-sequence. The circuit comprises selectively conductive electronic components coupled to the intermediate nodes.

Abstract: An electronic frequency mixer includes at least one transistor having a front gate, a back gate, a source, and a drain. The source is coupled to a node of application of a radio frequency input signal. The front gate is coupled to a node of application of a first periodic signal at a first frequency. The back gate is coupled to one of: a node of application of the first periodic signal or a node of application of a second periodic signal at the first frequency.

Abstract: The present disclosure is directed to shock and orientation detection for an electronic device. The shock detection detects shock events, such as an accidental drop of the device, and the orientation detection detects the orientation of the device at the time of the detected shock event. The detected shock event and orientations are stored in non-volatile memory. The shock and orientation detection are implemented in low power hardware without any host intervention, and may be implemented as an always-on feature that executes even when the device is in an off or low power state.

Abstract: A convolutional neural network includes convolution circuitry. The convolution circuitry performs convolution operations on input tensor values. The convolutional neural network includes requantization circuitry that requantizes convolution values output from the convolution circuitry.

Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

Abstract: In an embodiment a method for managing access rights of software tasks executed by a processing unit (CPU) using a cache memory containing execution data of the tasks in memory locations, each execution data having an attribute representative of a level of access right of the respective task, includes changing the attributes of the locations of the cache memory when the access rights of at least one task changes and retaining the execution data contained in the locations of the cache memory.

Abstract: In accordance with an embodiment, a system-on-chip includes: a memory circuit comprising a first memory region accessible with a first access right level and a second memory region accessible with the first access right level or a second access right level, at least one first peripheral having the first access right level, at least one second peripheral having the second access right level; and a direct memory access circuit configured to generate direct memory accesses, wherein the direct memory access circuit includes at least one first direct memory access controller having the first access right level and at least one second direct memory access controller having the second access right level.

Abstract: A controller for an electronic circuit that includes a first and a second switch is provided. The controller includes an event detector stage that receives logic electrical signals and a pulse generator circuit, which is coupled to the event detector stage and generates a dead time signal based on edges of the logic electrical signals detected by the event detector stage. The dead time signal includes pulses delimited by an edge of a first type and by a subsequent edge of a second type. A combinatorial sampling circuit generates a first and a second sampled preliminary signal. An update stage updates the values of the first and the second control signals at each pulse of the dead time signal based on the first and the second sampled preliminary signals, subsequently to the edge of the first type or the second type of the pulse of the dead time signal.

Abstract: A method for regulating voltage in an electronic device includes receiving, at a power stage, a gate voltage from an input terminal, and delivering an output voltage and an output current to a processing module based on the gate voltage. The gate voltage is compensated by comparing the output voltage with a reference voltage to produce a compensated gate voltage. The gate voltage compensation is sped by up stabilizing the output voltage during transitions between operational modes using a first compensation stage, decoupling a second compensation stage from the input terminal when a control signal is asserted to thereby precharge a compensation capacitor to an initial compensation voltage, and coupling the second compensation stage to the input terminal via a compensation resistor when the control signal is deasserted to thereby deliver the initial compensation voltage to the input terminal.

Abstract: Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.

Abstract: The disclosure concerns an electronic device comprising, stacked from a first surface to a second surface, a first stack and a second stack of two high electron mobility transistors, referred to as first and second transistor, the first and the second stack each comprising, from an insulating layer, interposed between the first and the second stack, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first and a second set of electrodes, the first and the second set of electrodes being each provided with a source electrode, with a drain electrode, and with a gate electrode which are arranged so that the first and the second transistor form a half-arm of a bridge.

Abstract: A circuit includes a clock input node, a first signal input node configured to receive a first modulated signal switching between a first DC voltage and a second DC voltage, a bias circuit, a first output node, a first capacitor, a second capacitor, and switching circuitry coupled to the first capacitor and the second capacitor. Control circuitry is configured to initially set the switching circuitry in a first configuration in response to the first modulated signal having the second DC voltage, thereby charging the first capacitor to the second DC voltage and charging the second capacitor to the first DC voltage, and subsequently set the switching circuitry in a second configuration in response to an edge detected in the clock signal, thereby producing the first threshold voltage at the first output node after charge redistribution taking place between the first and second capacitors.

Abstract: A first layer of a resin compatible with a laser direct structuring (LDS) is formed on a substrate and encapsulates a first integrated circuit. The substrate includes a first connection terminal electrically coupled to the first integrated circuit and a second connection terminal covered by the first layer. A first via is formed using LDS, the first via crossing the first layer and forming an electrical connection to the second connection terminal. A second integrated circuit is mounted over the first integrated circuit. A second layer of resin compatible with LDS is formed to encapsulate the second integrated circuit. A second via is formed using LDS, the second via crossing the second layer and forming an electrical connection to the first via.

Abstract: Disclosed herein is a method of reducing noise captured by an image sensor. The method includes affixing a bottom surface of a glass covering to the image sensor, permitting light to impinge upon the glass covering, and shaping the glass covering such that when the light that impinges upon the glass covering impinges upon a sidewall of the glass covering, the sidewall reflects the light on a trajectory away from the image sensor.

Abstract: In an embodiment a One-Time Programmable (OTP) memory controller includes a data register, a given number K of shadow-registers, wherein the number K is smaller than a given number N of memory slots of an OTP memory area, a communication interface configured to receive a read request requesting the data of a given memory slot and a control circuit configured to receive a preload start signal and a shadow-register preload enable signal, wherein the control circuit is configured to manage a preload phase and a data-read phase.

Abstract: An image sensor includes an array of pixels inside and on top of a substrate. A control circuit is configured to apply voltage potentials to the substrate. During a first phase, the control circuit applies a ground potential to the substrate. During a second phase, the control circuit applies a potential positive with respect to the ground potential to the substrate.

Abstract: One or more semiconductor dice are arranged on a substrate. The semiconductor die or dice have a first surface adjacent the substrate and a second surface facing away from the substrate. Laser-induced forward transfer (LIFT) processing is applied to the semiconductor die or dice to form fiducial markers on the second surface of the semiconductor die or dice. Laser direct structuring (LDS) material is molded onto the substrate. The fiducial markers on the second surface of the semiconductor die or dice are optically detectable at the surface of the LDS material. Laser beam processing is applied to the molded LDS material at spatial positions located as a function of the optically detected fiducial markers to provide electrically conductive formations for the semiconductor die or dice.

Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.

Abstract: In an embodiment a method includes compiling, by a processor in a compiling phase, a software program intended to be executed by the processor, the processor having secure and non-secure access right level execution contexts, and/or privileged and non-privileged access right level execution contexts and generating, in the compilation phase, instructions in machine language having an exclusively secure access right level when the instructions are intended to be executed in the secure access right level execution context, and instructions having a non-privileged access right level when the instructions are intended to be executed in the non-privileged access right level execution context.

Abstract: In accordance with an embodiment a method includes: receiving a slow down command to slow down a speed of a voice coil motor (VCM) in a hard disk drive; in response to receiving the slow down command, operating the VCM in a discontinuous mode by switching on and off a current through the VCM with a duty-cycle, wherein operating the VCM in the discontinuous mode reduces the speed of the VCM; sensing the speed of the VCM while operating the VCM in the discontinuous mode; and varying the duty-cycle of the switching on and off the current through the VCM as a function of the sensed speed of the VCM operated in the discontinuous mode, wherein varying the duty-cycle comprises reducing the duty-cycle in response to a reduction of the sensed VCM speed.