Patents Assigned to STMicroelectronics (Research & Development) Limite
  • Publication number: 20250167100
    Abstract: Packaged electronic device, having a C-shaped leadframe including a base section and a pair of transverse sections extending transversely to the base section. A first die and a second die have a first contact region at a first main surface and a second contact region at the second main surface; the first main surfaces of the first and the second dice are attached to a first face of the base section of the leadframe. A first lead is coupled to the second contact region of the first die and has a first external contact portion. A second lead is coupled to the second contact region of the second die and has a second external contact portion. A packaging mass surrounds the leadframe, the first lead and the second lead, embeds the first and the second dice and extends level with the base section and with the transverse sections of the leadframe as well as with the external contact portions of the leads.
    Type: Application
    Filed: October 16, 2024
    Publication date: May 22, 2025
    Applicant: STMicroelectronics International N.V.
    Inventor: Cristiano Gianluca STELLA
  • Publication number: 20250167682
    Abstract: A DC-DC switching converter includes an electrical network with an inductor, switches and first and second capacitors subject to first and second voltages. A control module generates first and second control signals to control the switches with a sequence of switching periods implementing, for each switching period, a phase succession including: an inductor charge phase having a first duration as a function of the first control signal; a first inductor discharge phase towards the first capacitor having a second duration as a function of the second control signal; and a second inductor discharge phase towards the second capacitor. The control module couples to the electrical network to form a signal vector including signals indicative of the first and second voltages and the current. A gain stage generates the first and second control signals by multiplying the signal vector by a gain matrix for the control module forming a linear-quadratic regulator.
    Type: Application
    Filed: November 12, 2024
    Publication date: May 22, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Andrea BARBIERI, Raffaele Enrico FURCERI, Aldo VIDONI, Mattia BONINI
  • Publication number: 20250165158
    Abstract: The present description concerns a method of configuration of a phase-change non-volatile memory, comprising the partitioning of said memory into a first set of one or a plurality of regions having a first maximum number of write cycles and a second set of one or a plurality of other regions having a second maximum number of write cycles greater than the first maximum number of write cycles, the first and second maximum number of write cycles being linked to different physical write parameters.
    Type: Application
    Filed: November 7, 2024
    Publication date: May 22, 2025
    Applicant: STMicroelectronics International N.V.
    Inventor: Jawad BENHAMMADI
  • Publication number: 20250158609
    Abstract: First digital-components are clocked by a system-clock, and second digital-components are clocked by a gated system-clock. A detection-module identifies detection-events and generates an event-flag in response. A digital-comparator generates a comparator-output based upon comparison of a count-value with a threshold, the comparator-output asserted when the count-value is less than the threshold and is deasserted when the count-value is equal-to or greater-than the threshold. A counter sets the count-value to a predetermined-value upon receipt of the event-flag, and, in response to assertion of the comparator-output, increments the count-value upon each successive rising-edge of the system-clock, but ceases when the comparator-output is deasserted.
    Type: Application
    Filed: December 15, 2023
    Publication date: May 15, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: John Kevin MOORE, Kenneth DARGAN, Angeliki DELAKOURA
  • Publication number: 20250160214
    Abstract: A thermoelectric unit includes a thermoelectric membrane having a first surface at a cavity in a layer of first thermally conductive material. The thermoelectric membrane has a second surface opposite to the first surface with second thermally conductive material arranged in contact with the second surface of the thermoelectric membrane. The thermoelectric membrane includes thermally sensitive material configured to generate via the Seebeck effect a thermoelectric signal indicative of the temperature difference between the second thermally conductive material and the first thermally conductive material. An insulating molding compound is molded onto the second thermally conductive material arranged in contact with the second surface of the thermoelectric membrane wherein mechanical stress develops in the thermoelectric membrane in response to molding. An encapsulation is provided at the second surface of the thermoelectric membrane.
    Type: Application
    Filed: November 11, 2024
    Publication date: May 15, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Antonio BELLIZZI, Fabrizio CREVENNA
  • Publication number: 20250158521
    Abstract: An integrated circuit chip includes a first pad coupled to an external power supply voltage by a conductive wire; a PMOS transistor coupling the first pad to an internal node; a second pad coupled to an external reference voltage by another conductive wire; and a capacitor coupling said first and second pads. A sensing circuit detects an increase in a drain-source resistance of the transistor. A control circuit supplies, during each switching of the transistor to the off state, a first current to the gate of the transistor until the sensing circuit detects the increase in the drain-source resistance, then supplies a second current lower than the first current.
    Type: Application
    Filed: November 8, 2024
    Publication date: May 15, 2025
    Applicant: STMicroelectronics International N.V.
    Inventor: Lionel CIMAZ
  • Publication number: 20250157860
    Abstract: Wafer level testing is performed on a wafer including integrated circuit dies, each integrated circuit die including a die pads, with each die pad covered by a protection layer. The wafer level testing includes, at a given die pad: puncturing through the protection layer with a distal end of a probe to make physical and electrical contact with the given die pad at a first location at the given die pad; performing a first electrical test of the integrated circuit die through the probe; horizontally translating after completion of the first electrical test; puncturing through the protection layer with the distal end of the probe to make physical and electrical contact with the given die pad at a second location, different from the first location, at the given die pad; and performing a second first electrical test of the integrated circuit die through the probe.
    Type: Application
    Filed: November 10, 2023
    Publication date: May 15, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Alberto PAGANI, Mattia DE NICOLA
  • Publication number: 20250160032
    Abstract: The present disclosure relates to an image sensor that includes first and second pixels. One or more transistors of the first pixel share an active region with one or more transistors of the second pixel.
    Type: Application
    Filed: January 14, 2025
    Publication date: May 15, 2025
    Applicants: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Crolles 2) SAS
    Inventors: Jeff M. RAYNOR, Frederic LALANNE, Pierre MALINGE
  • Publication number: 20250155913
    Abstract: A bandgap circuit includes: a first resistor receiving a voltage proportional to the temperature; a second resistor receiving a voltage complementary to absolute temperature; and a third resistor where the sum of the currents in the first and second resistors flows. Each of the second and third resistors comprises a fixed resistance part and N controllable resistance parts, with N greater than or equal to 2. Each controllable resistance part of the second resistor is associated with a corresponding controllable resistance part of the third resistor. A control circuit supplies, for each controllable resistance part, the same control signal to this controllable resistance part and its associated controllable resistance part.
    Type: Application
    Filed: November 11, 2024
    Publication date: May 15, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Thierry MASSON, Anthony QUELEN
  • Publication number: 20250158617
    Abstract: A clock signal detection circuit includes a first input that receives an always-on clock signal, and a second input that receives an activatable clock signal. A detection flip-flop circuit has a data input terminal that receives an always-high logic signal, a clock terminal that receives the always-on clock signal, a reset terminal that receives a reset signal, and a data output terminal that produces an asynchronous clock detection signal. The reset signal is asserted to reset the detection flip-flop circuit in response to the activatable clock signal being asserted, and the reset signal is de-asserted to prevent reset of the detection flip-flop circuit in response to the activatable clock signal being de-asserted. The asynchronous clock detection signal is passed to an output to provide a clock detection signal that is asserted to indicate that the activatable clock signal is absent.
    Type: Application
    Filed: November 6, 2024
    Publication date: May 15, 2025
    Applicant: STMicroelectronics International N.V.
    Inventor: Dorde CVEJANOVIC
  • Publication number: 20250157898
    Abstract: A leadframe includes first leads and second leads, wherein each lead of the first and second leads has an upper surface. First and second silver spots are provided on the upper surface of each lead of the first and second leads. An integrated circuit die has a front surface including first and second interconnection pads. A first pillar is mounted to each first interconnection pad, and second pillar is mounted to each second interconnection pad. The integrated circuit die is mounted in flip chip orientation to the leadframe with the first pillars soldered to the first silver spots and the second pillars soldered to the second silver spots. A resin body encapsulates the integrated circuit die mounted to the leadframe.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 15, 2025
    Applicant: STMicroelectronics International N.V.
    Inventor: Venero SANTAMARIA
  • Publication number: 20250159906
    Abstract: A method manufactures a memory including at least one first phase-change memory cell, each first cell including a resistive element, a first metal layer, and a second layer made of a phase-change material, the first layer being located between the resistive element and the second layer. The method includes the forming of a level including the resistive element, the forming of a third metal layer on the level, the etching of the third layer, and then the forming of the second layer.
    Type: Application
    Filed: November 1, 2024
    Publication date: May 15, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Alain OSTROVSKY, Jerome DUBOIS, Latifa DESVOIVRES, Simon JEANNOT, Christian BOCCACCIO
  • Patent number: 12299444
    Abstract: A system includes a memory and a processor coupled to the memory. The processor executes an instruction set having a word size. The processor includes arithmetic processing circuitry, which, in operation, executes arithmetic operations on operands having the word size. The arithmetic processing circuitry includes an arithmetic logic circuit (ALU) having an operand size smaller than the word size of the instruction set. The ALU, in operation, generates partial results of the arithmetic operations. A multiplexing network coupled to inputs of the ALU provides portions of the operands to the ALU. A shift register having the word size of the instruction set accumulates partial results generated by the ALU over a plurality of clock cycles and outputs results of the arithmetic operations based on the accumulated partial results.
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: May 13, 2025
    Assignee: STMicroelectronics International N.V.
    Inventor: Sofiane Landi
  • Patent number: 12302625
    Abstract: The disclosure concerns an electronic device provided with two high electron mobility transistors stacked on each other and having in common their source, drain, and gate electrodes. For example, each of these electrodes extends perpendicularly to the two transistors. For example, the source and drain electrodes electrically contact the conduction channels of each of the transistors so that said channels are electrically connected in parallel.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: May 13, 2025
    Assignees: STMicroelectronics France, STMicroelectronics International N.V.
    Inventors: Matthieu Nongaillard, Thomas Oheix
  • Patent number: 12298396
    Abstract: A method for estimating a flicker frequency of a light source includes: obtaining, with a time-of-flight sensor, a profile of a light signal emitted by a light source; performing spectral analysis on the profile of the light signal emitted by the light source; and estimating a flicker frequency of the light source based on the spectral analysis of the profile of the light signal emitted by the light source.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: May 13, 2025
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Giovanni Scozzola
  • Patent number: 12299214
    Abstract: The present disclosure is directed to lift-up gesture detection for electronic devices. An initial lift-up gesture is detected in response to an orientation change and a lift-up motion of the device being detected. The initial lift-up gesture is validated as a true lift-up gesture in a case where a shaking motion of the device is not being detected when the initial lift-up gesture is detected. If a shaking motion of the device is detected when the initial lift-up gesture is detected, the initial lift-up gesture is rejected.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: May 13, 2025
    Assignee: STMicroelectronics International N.V.
    Inventors: Stefano Paolo Rivolta, Federico Rizzardini, Lorenzo Bracco
  • Patent number: 12301240
    Abstract: In an embodiment, a circuit includes cascaded delay units arranged in a chain, each delay unit having an input-to-output delay time, wherein a first delay unit in the chain is configured to receive an input signal for propagating along the delay units in the chain, logic circuitry coupled to delay units in the chain, the logic circuitry configured to generate a clock signal as a logic combination of signals input to and output from the delay units in the chain and feedback circuitry configured to supply to the first delay unit in the chain a feedback signal, the feedback circuitry including a first feedback signal path from a last delay unit in the chain to the first delay unit in the chain and a second feedback signal path from an intermediate delay unit in the chain to the first delay unit in the chain, the intermediate delay unit arranged between the first delay unit in the chain and the last delay unit in the chain.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: May 13, 2025
    Assignee: STMicroelectronics S.r.l.
    Inventor: David Vincenzoni
  • Patent number: 12301111
    Abstract: A supply node receives supply voltage and an output node provides a regulated output voltage to a load. A switching transistor is coupled between the supply and output nodes. The switching transistor is controlled by a drive signal generated by a control circuit to control switching activity. The control circuit includes circuitry to sense a feedback voltage indicative of the regulated output voltage and a comparator generating a comparison logic signal dependent on a comparison of the feedback voltage to a reference. A logic circuit generates a skip signal in response to the comparison logic signal. A counter generates a termination signal. Signal processing circuitry controls the switching activity by asserting the drive signal as a function of the skip signal and the termination signal.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: May 13, 2025
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Bertolini, Alberto Cattani, Alessandro Gasparini
  • Patent number: 12300585
    Abstract: Disclosed herein is a method for manufacturing a semiconductor product package. The method includes arranging a leadframe with one or more leads such that each lead has an inner end facing a portion of a die-pad, attaching a semiconductor chip to the die-pad, attaching a first electrically conductive mass to the die-pad such that it is aligned with the inner end of a lead protruding over the die-pad, attaching an electrical component to the first electrically conductive mass such that a longitudinal axis of the electrical component is arranged traverse to the die-pad, and coupling a second electrically conductive mass between a termination of the electrical component and the inner end of the lead.
    Type: Grant
    Filed: September 18, 2023
    Date of Patent: May 13, 2025
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alberto Arrigoni, Giovanni Graziosi, Aurora Sanna
  • Patent number: 12301156
    Abstract: A method for controlling a BLDC motor includes controlling the rotational speed or position of the BLDC motor based on a position of the rotor of the motor. The BLDC motor is driven by a three-phase inverter. A PWM signal is generated for three PWM phases, each including a pair of complementary signals with dead-time and having a duty cycle based on the current position of the rotor. The complementary signals are supplied to a respective high side and low side switch of each of three arms of the three-phase inverter, and a zero-crossing time measurement is performed on each of the back electromotive forces. Corresponding signals are obtained indicating the zero-crossing times. Trigger signals are generated, and the occurrence of a time interval corresponding to the dead time in the respective PWM phase is identified. The zero-crossing time measurement is performed during the occurrence of the dead-time.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: May 13, 2025
    Assignee: STMicroelectronics S.r.l.
    Inventor: Giuseppe D'Angelo