Patents Assigned to STMicroelectronics (Research & Development) Limite
  • Publication number: 20250178886
    Abstract: A microelectromechanical membrane sensor includes: a supporting body, containing semiconductor material and having a recess in a face; a platform, housed in the recess at a distance from the supporting body; a flexure, connecting the platform to the supporting body and configured to keep the platform suspended in the recess. A gap extends between the supporting body, the platform and the flexure. A membrane is housed in the platform and delimits a buried cavity incorporated in the platform. A sealing strip extends on the supporting body, on the platform and on the flexure along the gap.
    Type: Application
    Filed: November 19, 2024
    Publication date: June 5, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Mark Andrew SHAW, Lorenzo BALDO, Filippo DANIELE, Silvia ADORNO
  • Publication number: 20250185390
    Abstract: A pixel includes a first electrode layer on an exposed surface of an interconnection structure and in contact with a conductive element of the interconnection structure. An insulating layer extends over the first electrode layer and includes opening crossing through the insulating layer to the first electrode layer. A second electrode layer is on top of and in contact with the first electrode layer and the insulating layer in the opening. A film configured to convert photons into electron-hole pairs is on the insulating layer, the second electrode layer and filling the opening. A third electrode layer covers the film.
    Type: Application
    Filed: February 12, 2025
    Publication date: June 5, 2025
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Thierry BERGER, Stephane ALLEGRET-MARET
  • Publication number: 20250181105
    Abstract: According to one aspect, provision is made of a timing method implemented by a computer system comprising: a central processing unit, an external clock circuit comprising a counter, the counter being configured to increment or decrement its value with each clock stroke of the external clock circuit over a range of values corresponding to one millisecond, the timing method comprising: defining a maximum number of transitions of a bit to be monitored of the counter value corresponding to a desired waiting delay, monitoring transitions of the bit to be monitored of the counter value so as to achieve the timing until the number of performed transitions of the bit to be monitored reaches the defined maximum number of transitions.
    Type: Application
    Filed: November 19, 2024
    Publication date: June 5, 2025
    Applicant: STMicroelectronics International N.V.
    Inventor: Philippe CHERBONNEL
  • Publication number: 20250178885
    Abstract: A microelectromechanical motion sensor device is described, provided with: a base substrate having a front surface with extension in a horizontal plane; and a sensing structure arranged above the base substrate, for sensing components of a motion quantity along respective sensing axes. The sensing structure is provided with: a housing element integrally coupled above the front surface of the base substrate and internally defining a cavity; a single mobile mass arranged inside the cavity; an elastic supporting arrangement arranged above the mobile mass, with main extension in a plane overlying the mobile mass to elastically support the mobile mass inside the cavity, so that it is suspended above the front surface of the base substrate and performs, due to inertial effect, a respective sensing movement in response to each of the components of the motion quantity; and a sensing electrode arrangement, capacitively coupled to the mobile mass for sensing the components of the motion quantity.
    Type: Application
    Filed: November 26, 2024
    Publication date: June 5, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Massimiliano PESATURO, Bruno MURARI, Stefano BOSCO, Manuel RIANI, Paolo PESENTI
  • Publication number: 20250185276
    Abstract: The disclosure concerns a device which comprises a stack of two high electron mobility transistors, referred to as first and second transistor, separated by an insulating layer and each provided with a stack of semiconductor layers respectively referred to as first stack and second stack, the first and the second stack each comprising, from the insulating layer to, respectively, a first and a second surface, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first set of electrodes and a second set of electrodes, the first and the second set of electrodes each comprising a source electrode, a drain electrode, and a gate electrode which are arranged so that the first and the second transistor are electrically connected head-to-tail.
    Type: Application
    Filed: February 5, 2025
    Publication date: June 5, 2025
    Applicant: STMicroelectronics France
    Inventors: Matthieu NONGAILLARD, Thomas OHEIX
  • Publication number: 20250180597
    Abstract: An inertial structure is elastically coupled through a first elastic structure to a supporting structure so as to move along a sensing axis as a function of a quantity to be detected. The inertial structure includes first and second inertial masses which are elastically coupled together by a second elastic structure to enable movement of the second inertial mass along the sensing axis. The first elastic structure has a lower elastic constant than the second elastic structure so that, in presence of the quantity to be detected, the inertial structure moves in a sensing direction until the first inertial mass stops against a stop structure and the second elastic mass can move further in the sensing direction. Once the quantity to be detected ends, the second inertial mass moves in a direction opposite to the sensing direction and detaches the first inertial mass from the stop structure.
    Type: Application
    Filed: October 11, 2024
    Publication date: June 5, 2025
    Applicant: STMicroelectronics S.r.l.
    Inventors: Gabriele GATTERE, Francesco RIZZINI, Alessandro TOCCHIO
  • Publication number: 20250178889
    Abstract: A process for manufacturing a combined microelectromechanical device envisages: forming, in a sensor wafer, at least a first and a second microelectromechanical structures, at a main surface; forming, in a cap wafer, at least a first and a second cavities, at a respective main surface; forming a getter region inside the first cavity; bonding the main surfaces of the sensor and cap wafers by means of a bonding region, to define a first and a second hermetic environments for the microelectromechanical structures at different pressure values. A raised frame is formed, before the bonding step, in such a way as to be located around the first cavity; the bonding region determines the bonding of the sensor and cap wafers at the raised frame and the definition of the first hermetic environment associated with the first cavity, in a time interval prior to hermetic closure of the second cavity.
    Type: Application
    Filed: November 25, 2024
    Publication date: June 5, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Anna GUERRA, Lorenzo CORSO, Federico VERCESI, Alessandro LUBERTO, Giorgio ALLEGATO
  • Patent number: 12322603
    Abstract: Semiconductor chips are arranged on an elongated substrate and encapsulated by an insulating encapsulation. Electrically conductive formations and electrically conductive plating lines are plated on the insulating encapsulation using, for example, Laser Direct Structuring (LDS) or Direct Copper Interconnect (DCI) material. The electrically conductive plating lines include first transverse plating lines as well as second plating lines branching out from the first plating lines towards the electrically conductive formations. A first partial cutting step is then performed to form grooves which remove the first plating lines. An insulating material is dispensed in the grooves to encapsulate the end portions of the second plating lines. A second cutting step median along the groove and through the elongate substrate is performed to produce singulated semiconductor devices (such as “die pad up” Quad-Flat No-lead (QFN) packages). End portions of the second plating lines are encapsulated by the insulating material.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: June 3, 2025
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Tiziani, Antonio Bellizzi
  • Patent number: 12323060
    Abstract: A buck-boost converter circuit includes a mode selection circuit that asserts a buck enable signal if an input voltage is higher than a lower threshold, and asserts a boost enable signal if the input voltage is lower than an upper threshold. A control circuit asserts a buck PWM signal upon a pulse in a buck clock and de-asserts the buck PWM signal if a buck ramp is higher than a buck control signal, and it keeps the buck PWM signal asserted if the buck enable signal is de-asserted. The control circuit asserts a boost PWM signal upon a pulse in a boost clock and de-asserts the boost PWM signal if a boost ramp is higher than a boost control signal, and it keeps the boost PWM signal de-asserted if the boost enable signal is de-asserted.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: June 3, 2025
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nunzio Greco, Osvaldo Enrico Zambetti, Ranieri Guerra, Francesca Giacoma Mignemi
  • Patent number: 12323573
    Abstract: An electronic device includes a pixel array having a plurality of rows with active imaging pixels, and at least one row with test pixels. Each of the test pixels includes a test voltage generation circuit generating a test voltage, a switching circuit receiving the test voltage and an image pixel output signal and passing the test voltage as output when in a test mode, a comparison circuit receiving the output from the switching circuit and an analog to digital conversion signal and asserting a counter reset signal when the output from the switching circuit and the analog to digital conversion signal are equal in voltage, and a counter beginning counting at a beginning of each test cycle within the test mode, stopping counting upon assertion of the counter reset signal, and outputting its count upon stopping counting. The count is proportional to the test voltage when in the test mode.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: June 3, 2025
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Hong Chean Choo, Lookah Chua, Wai Yin Hnin
  • Patent number: 12324250
    Abstract: The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the doping level of the germanium increasing as the distance from the p-n junction increases.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: June 3, 2025
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Younes Benhammou, Dominique Golanski, Denis Rideau
  • Patent number: 12321739
    Abstract: According to one aspect, a method adds an additional function to a computer program installed on a microcontroller, the computer program using a table configured to associate an identifier of the additional function with a pointer to a memory address. The method includes the microcontroller obtaining a compiled code of the additional function and an identifier of this additional function, the microcontroller recording the compiled code of the additional function in a section of a memory, and recording in memory a pointer in the table, the pointer being aimed at the address of the memory section in which the compiled code of the additional function is recorded, the pointer being associated in the table with the identifier of the additional function.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: June 3, 2025
    Assignee: STMicroelectronics (Grand Ouest) SAS
    Inventor: Frederic Ruelle
  • Patent number: 12323136
    Abstract: A control device includes a triac and a first diode that is series-connected between the triac and a first terminal of the device that is configured to be connected to a cathode gate of a thyristor. A second terminal of the control device is configured to be connected to an anode of the thyristor. The triac has a gate connected to a third terminal of the device that is configured to receive a control signal. The thyristor is a component part of one or more of a rectifying bridge circuit, an in-rush current limiting circuit or a solid-state relay circuit.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: June 3, 2025
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Romain Pichon, Yannick Hague
  • Patent number: 12322977
    Abstract: A wireless device includes an energy harvester and an energy storage that operate in a sequence of energy harvesting cycles to alternately harvest energy and release energy for supplying the wireless device. The wireless device also includes a processing circuit and a wireless communication circuit. A configuration method for the wireless device includes first step where a base station receives a signal from the wireless device indicating wireless communication circuit entry into a receiving operation mode. In a second step, the base station transmits configuration data to the wireless device. The received configuration data is temporarily stored in a memory area of the wireless communication circuit. In a third step, the temporarily stored configuration data is transmitted from the wireless communication circuit to the processing circuit for storage in a memory area. The second and third steps are carried out during distinct energy harvesting cycles of the wireless device.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: June 3, 2025
    Assignee: STMicroelectronics S.r.l.
    Inventor: Roberto La Rosa
  • Patent number: 12323789
    Abstract: The present description discloses a secure element and a communication method, configured to implement at least one first application, and including a circuit configured to record routing data and a list and parameters of communication protocols compatible with the first application, verify the compatibility of a first communication protocol used by first messages intended for the first application with the protocols of the list, convert the first messages into second messages by using a second communication protocol in response to the first protocol not being compatible with at least one of the protocols of the list, and direct the second messages to the first application by using the routing data of the first application.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: June 3, 2025
    Assignees: STMicroelectronics (ROUSSET) SAS, STMicroelectronics Belgium
    Inventors: Olivier Van Nieuwenhuyze, Alexandre Charles
  • Patent number: 12322684
    Abstract: A substrate includes electrically-conductive tracks. A semiconductor chip is arranged on the substrate and electrically coupled to selected ones of the electrically-conductive tracks. Containment structures are provided at selected locations on the electrically-conductive tracks, where the containment structures have respective perimeter walls defining respective cavities. Each cavity is configured to accommodate a base portion of a pin holder. These pin holders are soldered to the electrically-conductive tracks within the cavities defined by the containment structures. Each containment structure may be formed by a ring of resist material configured to receive solder and maintain the pin holders in a desired alignment position.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: June 3, 2025
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Pte Ltd
    Inventors: Roberto Tiziani, Laurent Herard
  • Patent number: 12324251
    Abstract: A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.
    Type: Grant
    Filed: February 27, 2024
    Date of Patent: June 3, 2025
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Denis Rideau, Dominique Golanski, Alexandre Lopez, Gabriel Mugny
  • Publication number: 20250173420
    Abstract: A method of authentication of a first device to a second device uses a signature of an analog signal of the first device. The signature corresponds to a time variation of at least one physical quantity associated with the analog signal during the implementation of at least one specific operation. The at least one specific operation may be an implementation of an electronic function or a program.
    Type: Application
    Filed: November 20, 2024
    Publication date: May 29, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Michael PEETERS, Francois DE ROCHEBOUET, Jean-Louis MODAVE
  • Publication number: 20250176235
    Abstract: A method for manufacturing a SiC-based electronic device, comprising the steps of: implanting, on a front side of a solid body made of SiC having a conductivity of an N type, dopant species of a P type thus forming an implanted region, which extends in the solid body starting from the front side and has a top surface coplanar with the front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region to temperatures comprised between 1500° C. and 2600° C. so as to form a carbon-rich electrical-contact region at the implanted region. The carbon-rich electrical-contact region forms an ohmic contact.
    Type: Application
    Filed: January 30, 2025
    Publication date: May 29, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Simone RASCUNÁ, Mario Giuseppe SAGGIO, Giovanni FRANCO
  • Publication number: 20250174616
    Abstract: The present disclosure is directed to embodiments of optical sensor packages. For example, at least one embodiment of an optical sensor package includes a light-emitting die, a light-receiving die, and an interconnect substrate within a first resin. A first transparent portion is positioned on the light-emitting die and the interconnect substrate, and a second transparent portion is positioned on the light-receiving die and the interconnect substrate. A second resin is on the first resin, the interconnect substrate, and the first and second transparent portions, respectively. The second resin partially covers respective surfaces of the first and second transparent portions, respectively, such that the respective surfaces are exposed from the second resin.
    Type: Application
    Filed: January 28, 2025
    Publication date: May 29, 2025
    Applicant: STMicroelectronics Pte Ltd
    Inventor: Jing-En LUAN