Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

Abstract: The disclosure concerns a method including the steps of: a) providing a structure comprising a semiconductor substrate and, on the side of a first surface of the substrate, at least one first trench filled with an insulating material, vertically extending in the substrate; b) forming, by anisotropic etching from a second surface of the semiconductor substrate opposite to the first surface, at least one second trench vertically extending in the substrate and emerging onto the at least one first trench; and c) widening the at least one second trench by isotropic etching.

Abstract: A deep trench isolation structure is formed in a semiconductor material body by opening first and second trenches. The sidewalls and bottoms of the first and second trenches are then lined with an insulating material. A halogen-based polymer material is then deposited to cover at least an upper portion of the insulation material in the first trench without covering a portion insulation material at the bottom of the first trench and further cover the insulation material at the sidewalls and bottom of the second trench. An etch process is then used to remove the portion of the insulation material at the bottom of the first trench and the polymer material is removed from both the first trench and second trench. The trenches are then filled with polysilicon to form a substrate plug in the first trench and a field plate electrode in the second trench.

Abstract: Process for manufacturing electronic components with wettable flanks from a substrate covered by connection terminals and in which chips are formed, the process comprising the following steps: a) solder connection pads to the connection terminals, b) coat the connection pads with a layer of insulating resin, c) thin the insulating resin layer until it reaches the core of the connection pads, d) form cavities by removing part of the connection pads and part of the insulating resin layer, so as to make part of the flanks of the components accessible, e) deposit a layer of conductive material on the flanks of the components and on the connection pads, f) separate the chips.

Abstract: A power module including a rigid-flexible PCB that exits from a resin molding case, and includes a first PCB region having a stacked structure of piled up layers; a second PCB region having said stacked structure, further locally delimited at a first side by a top stiffening element and at a second opposite side by a bottom stiffening element; and a third PCB region having said stacked structure without the top and bottom stiffening elements. The top and bottom stiffening elements extend at a lateral surface of the molding case, where the PCB exits from the molding case, and are configured to locally increase the rigidity of the PCB with respect to regions of the PCB 20 where said top and bottom stiffening elements are absent. A power module and method of manufacturing the power module is also provided.

Abstract: The present disclosure is directed to a MEMS device having a first and a second actuator element, of piezoelectric type and a first and a second arm. The first and a second actuator element are configured to generate respective alternate, approximately linear, movements of an own end portion along a first and, respectively, a second direction, the second direction transverse to the first direction. The first arm has a first end rigid with the end portion of the first actuator element. The second arm extends transversally to the first arm and has a first end coupled rigid with the end portion of the second actuator element and a second end coupled rigid with the first arm. The first and the second actuator elements are configured to be driven in an offset manner, so that the second end of the first arm performs a movement along a closed line.

Abstract: Disclosed is an apparatus including a plurality of channels that drive one or more electrical loads and a control module that generates control signals to operate at least one channel in the plurality of channels, an electronic fuse that monitors one or more operating parameter in a respective channel and detects anomalous conditions in that channel based on the parameter(s) monitored, and a parallel-mode block that defines one or more sets of channels including two or more channels configured to drive a same load. The control module receives from the parallel-mode block parallel-mode management control signals and operates the channels in the set of channels based on parallel-mode management control signals received by the parallel-mode block. The electronic fuse makes the channels in the set of channels non-conductive in response to an anomalous condition detected even in just one channel in the set.

Abstract: At start-up of a microelectromechanical system (MEMS) gyroscope, the drive signal is inhibited, and the phase, frequency and amplitude of any residual mechanical oscillation is sensed and processed to determine a process path for start-up. In the event that the sensed frequency of the residual mechanical oscillation is a spurious mode frequency and a quality factor of the residual mechanical oscillation is sufficient, an anti-phase signal is applied as the MEMS gyroscope drive signal in order to implement an active dampening of the residual mechanical oscillation. A kicking phase can then be performed to initiate oscillation. Also, in the event that the sensed frequency of the residual mechanical oscillation is a resonant mode frequency with sufficient drive energy, a quadrature phase signal with phase lock loop frequency control and amplitude controlled by the drive energy is applied as the MEMS gyroscope drive signal in order to induce controlled oscillation.

Abstract: A device includes input data lines associated with a first time domain and output data lines associated with a second time domain. Synchronizing circuitry is coupled between the input data lines and output data lines. The synchronizing circuitry is driven by a synchronizing clock signal generated by clock generating circuitry. The clock generating circuitry is coupled to the input data lines and the synchronizing circuitry. In operation, the clock generating circuitry detects signal transitions on the plurality of input data lines. The clock generating circuitry generates the synchronizing clock signal that drives the synchronizing circuitry based on detected transitions, a clock signal of the first time domain, and a clock signal of the second time domain.

Abstract: A DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a first path coupled between the input node and a first output node at which a first output voltage is generated, and a second path coupled between the input node and a second output node at which a second output voltage is generated. The DC-DC boost converter operates in a first operating phase where the first path boosts the first output voltage and where the second path is kept from boosting the second output voltage by the second path being coupled to the first path, and operates in a second operating phase where the second path boosts the second output voltage and where the first path is kept from boosting the first output voltage by the second path not being coupled to the first path.

Abstract: A first input node receives a first input signal and a second input node receives a second input signal. The first and second input signals are in phase quadrature. An edge detector circuit senses the first input signal and produces a pulsed signal indicative of edges detected in the first input signal. A pulse skip and reset circuit senses the pulsed signal and the second input signal, and produces a reset signal indicative of pulses detected in the pulsed signal while the second input signal is de-asserted. A sampling circuit senses the second input signal and the reset signal, and produces an output signal that is deasserted in response to assertion of the second input signal and is asserted in response to a pulse being detected in the reset signal.

Abstract: The present description concerns an operating method of a non-volatile memory, comprising the validation of a transaction, requesting a modification of a value of configuration of a sector of the memory, after comparison of the attributes of the transaction with access attributes of said sector of said memory.

Abstract: The disclosure relates to an optoelectronic device comprising in a stack: one reflection polarizing filter, one phase-shifting element configured to add a ?/4 phase shift in polarization, one active region, one reflector, so that the light radiation rays reflected by the reflector and passing through the phase-shifting element exhibit a new polarization phase-shifted by ?/2 with respect to their initial polarization, the rays then being reflected anew by the polarizing filter in the direction of the active region.

Abstract: An electronic component includes a gate structure over a semiconductor layer. The gate structure is insulated from the semiconductor layer and includes a layer made of a magnetic material. The electronic component may form a FET transistor, a MOSFET transistor, a SET transistor, a gated diode, a gated MOS structure, or a gated quantum dot.

Abstract: A process for a slave device on a serial data bus to make an in-band interrupt request to a master device includes checking whether a backoff time stored by a backoff timer has expired. When the backoff time has not expired, the slave device refrains from initiating the in-band interrupt request to the master device in response to a start condition on the serial bus. However, when the backoff time has expired, the slave device is permitted to initiate the in-band interrupt request to the master device in response to the start condition on the serial bus.

Abstract: A device includes a leadframe with a semiconductor die having a first side facing and electrically coupled to the leadframe and a second side facing away from the leadframe. An encapsulation body containing laser direct structuring (LDS) material covers the semiconductor die and has an outer surface opposite the leadframe. Metal vias are formed through the LDS material between the outer surface and the second side of the semiconductor die, and a metal pad is formed at the outer surface. The metal vias and pad create a thermal dissipation path. The semiconductor die may be mounted in a flip-chip configuration and connected to the leadframe through metal pillars. The metal vias and pad may be formed by laser-activating the LDS material followed by copper plating. The device can be configured as a Quad Flat No-leads (QFN) package, and a heat sink may be mounted on the metal pad.

Abstract: A half bridge circuit includes two GaN high electron mobility transistors (HEMT). A driver circuit generates a high side and low side driver signals corresponding to square wave. A driver deadtime is the period between during which both driver signals are low. A half bridge adjustment circuit is coupled between the driver and the half bridge circuit and generates a modified high side driver signal and a modified low side driver signal, each including a transition from a low voltage to an intermediate voltage during the corresponding deadtime and a transition from the intermediate voltage to a high voltage at an end of the corresponding deadtime. The half bridge adjustment circuit drives the gate terminals of the high side and low side transistors with the modified high side and low side driver signals.

Abstract: A substrate includes a center portion and a peripheral portion connected to the center portion by a flexible coupling region. A first die is mounted to an upper surface of the substrate at the center portion and a second die is mounted to the upper surface of the substrate at the peripheral portion. A heatsink includes a base plate, fins extending from an upper surface of the base plate and tabs extending from a lower surface of the base plate. The tabs of the heatsink are mounted to the upper surface of the substrate at the center portion, and the lower surface of the base plate is thermally coupled to a back of the first die. The peripheral portion is folded relative to the center portion at the flexible coupling region. An outer surface of the fin of the heatsink is thermally coupled to a back of the second device.

Abstract: The present description concerns a method of manufacturing an electronic circuit comprising, in the order, the forming on a semiconductor substrate comprising a surface of at least one conductive pad extending over the surface and having sides inclined with respect to the surface, the forming of a first insulating layer on the pad, the deposition of a resin layer and the forming of an opening in the resin layer exposing the entire pad, the plasma etching of the first insulating layer in the opening, which results in the forming of first compounds on the etched edges of the first insulating layer and of second compounds on the pad, the removal of the resin layer, the removal of the first compounds, the removal of the second compounds, and the forming of a second insulating layer on the pad.

Abstract: A process that helps ensure uniform height of conductive structures formed among intermetal dielectric layers of a wafer. When a metal layer is deposited on a first intermetal dielectric layer, a sealing layer is formed on the metal layer either before or after the metal layer is patterned to form metal interconnect structures. A first interlevel dielectric sub-layer is then formed on the sealing layer. A chemical mechanical planarization (CMP) process is then performed on the first interlevel dielectric sub-layer using the sealing layer as an etch stop. A second interlevel dielectric sub-layer is then formed on the first interlevel dielectric sub-layer.