Abstract: A pressure-sensor includes a substrate with a cavity therein and a membrane suspended over the cavity. The cavity is connected to external air pressure so a change in external air pressure causes out-of-plane movement of the membrane. A frame suspended over the membrane includes a segment connected to the membrane but disconnected from other frame portions. A projection extends from the frame. A first spring is connected to the projection, a second spring is connected to the segment, and an end portion connects the springs so out-of-plane movement of the membrane applies out-of-plane force to the second spring, which is transferred to the first spring by the end portion and translated to an in-plane force by the first spring and applied to the projection. This causes lateral sliding movement of the frame with respect to the substrate. A capacitive-sensor detects sliding movement of the frame with respect to the substrate.

Abstract: A hybrid QFN and QFP integrated circuit package includes a leadframe with first second die pads supporting first and second integrated circuits, respectively. The leadframe further includes QFN conductive pads QFP conductive leads. A package housing encapsulates the first and second die pads, the first and second integrated circuits mounted thereto, the QFN conductive pads, and proximal ends of the QFP conductive leads. Distal ends of the QFP conductive leads extend away from side edges of the package housing. Bottom surfaces of the QFN conductive pads are exposed at a bottom surface of the package housing. The QFN conductive pads are located between the first and second die pads.

Abstract: A manufacturing process provides for: forming a semiconductor body of silicon carbide, having a front surface; performing a localized ion implantation to form implanted regions in implant portions in the semiconductor body. The step of performing a localized ion implantation provides for: forming damaged regions at the front surface, separated from each other by the implant portions in a direction parallel to the front surface; performing a channeled ion implantation, for implanting doping ions within the semiconductor body and forming the implanted regions at the implant portions of the semiconductor body. The channeled ion implantation is performed in a self-aligned manner with respect to the damaged regions, which represent damaged regions of the silicon-carbide crystallographic lattice such as to block a propagation of the channeled ion implantation along a vertical axis orthogonal to the front surface, in a depth direction of the semiconductor body.

Abstract: A semiconductor substrate has a substrate trench extending from a front surface and including a lower part and an upper part. A first insulation layer lines the substrate trench, and a first conductive material is insulated from the semiconductor substrate by the first insulating layer to form a transistor field plate electrode. A gate trench in the first insulation layer defines an integral part of the first insulating layer surrounding the first conductive material in an upper part of the substrate trench. A second insulating layer lines the semiconductor substrate at the upper part of the substrate trench in the gate trench. A second conductive material fills the gate. The second conductive material forms a transistor gate electrode that is insulated from the semiconductor substrate by the second insulating layer and further insulated from the first conductive material by the integral part of the first insulating layer.

Abstract: An integrated circuit includes a sequential logic circuit and a circuit configured to change operation as a function of state output signals provided by state flip-flops of the sequential logic circuit. With a test mode signal asserted, a test circuit writes and reads the content of the state flip-flops in order to test the operation of the sequential logic circuit. A processing system includes at least one storage circuit interposed between the circuit and a respective state output signal. Each storage circuit receives the respective state output signal and provides a modified state signal to the circuit. When the test mode signal is de-asserted, the storage circuit provides the received state output signal in a transparent manner to the circuit and stores the received state output signal to a storage element. When the test mode signal is asserted, the storage circuit provides the stored state output signal to the circuit.

Abstract: An embodiment method includes rectifying a back electromotive force of a spindle motor in a hard disk drive and energizing a voice coil motor in the hard disk drive using the rectified back electromotive force of the spindle motor via a voice coil motor power stage to retract a head of the hard disk drive to a park position. The head is retracted by moving the head towards the park position during a first retract phase and retaining the head in the park position during a second retract phase by applying a bias voltage to the voice coil motor power stage during a bias interval of the second retract phase. The method also includes producing a saturation signal indicative of onset of saturation in the voice coil motor power stage and controlling the bias voltage during the second retract phase.

Abstract: A power switch device includes a first terminal intended to be connected to a source of a first supply potential, a second terminal configured to supply a second potential, and a third terminal intended to be connected to a second source of a third supply potential. The device includes a first PMOS transistor having a source connected to the second terminal and a drain connected to the third terminal, a second PMOS transistor having a source connected to the second terminal, and a third PMOS transistor having a source connected to the first terminal and a drain connected to the drain of the second transistor. A control circuit generates gate control signals to control operation of the first, second and third PMOS transistors dependent on the first, second, and third supply potentials.

Abstract: A contactless communication device includes an electronic integrated circuit chip and an antenna coupled to the electronic integrated circuit chip to supply an electric signal for powering the electronic integrated circuit chip. An ambient luminosity detection element is coupled to the electronic integrated circuit chip. An ambient luminosity level measured by the ambient luminosity detection element is supplied to the electronic integrated circuit chip for comparison to a darkness threshold. A contactless communication is authorized only when the measured ambient luminosity level is greater than the darkness threshold.

Abstract: The present disclosure relates to a read-out circuit comprising N inputs configured to be connected to N respective outputs of a pixel array of an image sensor, with N being an integer strictly greater than 1; and N analog-to-digital converters organized in K groups, with K being an integer strictly greater than 1 and strictly less than N, and each having a first input coupled to a respective one of the N inputs and a second input. In each group, the second inputs of the analog-to-digital converters of the group are connected together, electrically decoupled from the second inputs of the analog-to-digital converters of the other groups, and configured to receive a first reference signal that is identical for all the analog-to-digital converters of the group.

Abstract: In an embodiment a method includes generating a low-frequency clock signal having a first frequency, in a standby mode and in a run mode of the CPU, generating a high-frequency clock signal having a second frequency higher than the first frequency, in the run mode, updating a value of the reference time base at each period of the low-frequency clock signal in the standby mode, and accessing the counter register with the high-frequency clock signal in the run mode.

Abstract: A method of making a MEMS device including forming a mirror stack on a handle layer, applying a first bonding layer to the mirror stack, and disposing a substrate on the first bonding layer. The handle layer is removed and a second bonding layer is applied. A cap layer is disposed on the second bonding layer. The mirror stack is formed by disposing a silicon layer on the handle layer, disposing a first insulating layer on the silicon layer, etching portions of the first insulating layer, and depositing a first conductive layer on the first insulating layer. The formation also includes depositing a second insulating layer on the first conductive layer, a portion of the second insulating layer to expose a portion of the first conductive layer exposed, and forming a conductive pad on the exposed portion of the first conductive layer.

Abstract: The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP) or a package containing a semiconductor die, with a die embedded within a substrate that is surrounded by an elastomer. The package includes nonconductive layers on surfaces of the substrate and the elastomer as well as conductive layers and conductive vias that extend through these layers to form electrical connections in the package. The package includes surfaces of the conductive material, which may be referred to as contacts. These surfaces of the conductive material are exposed on both sides of the package and allow the package to be mounted within an electronic device and have other electronic components coupled to the package, or allow the package to be included in a stacked configuration of semiconductor dice or packages.

Abstract: A Single Input Dual Output converter includes a first switch coupling an input to a first inductor terminal, a second switch coupling a second inductor terminal to ground, a third switch coupling the second inductor terminal to a positive output, and a fourth switch coupling the first inductor terminal to a negative output. During time-shared control, the negative and positive outputs are independently served by conversion cycles. Each conversion cycle includes: a positive phase with a positive charge phase (closing only the first and second switches), followed by an additional phase (closing only the first and third switches for a given time duration), and followed by a positive discharge phase (closing only the third and fourth switches). Each conversion cycle further includes a negative phase with a negative charge phase (closing only the first and second switches) followed by a negative discharge phase (closing only the second and fourth switches).

Abstract: An audio electronic system includes a DC switching converter comprising first and second Zeta converters, each comprising an input stage, an output stage, a first switching stage, and a second switching stage. The input stage of each Zeta converter comprises a respective input inductor having a first terminal electrically coupled to the respective first switching stage. The input inductors of the input stages of the first and second Zeta converters are magnetically coupled in such a way that when current enters the terminal of the input inductor of the first Zeta converter that is coupled to the first switch stage of the first Zeta converter, a voltage induced by the coupled current is positive at the terminal of the input inductor of the second Zeta converter that is coupled to the first switching stage of the second Zeta converter.

Abstract: The present disclosure is directed to a voltage driver, where a combination of first and second resistance blocks controls a differential voltage swing on the outputs of the voltage driver. Variations of an input voltage are compensated by adding different values of the first resistance block to the second resistance block, while keeping a summation of the first and second resistance blocks at a constant value. Three different circuit diagrams are disclosed to generate these different resistances. In each circuit diagram, one or more control signals change the resistance of the combination of first and second resistance blocks. In some embodiments, the value of the second resistance block is changed by the first resistance block to maintain an impedance matching between a transmitter and a receiver, while changing of the first resistance block compensates for the differential voltage swing.

Abstract: A memory cell is formed by a PIN diode having three contacts. A breakdown voltage is applied to break down a gate oxide arranged between a region of the PIN diode and a substrate region. The breakdown or non-breakdown state of the gate oxide is determined by applying a read voltage between the anode and the cathode of the diode and determining the value of the corresponding current flowing in the diode.

Abstract: A method includes executing an application of a scripting language. The application of the scripting language uses first and second packages of an application programming interface (API). The first and second packages extend to each other. The method includes, from a class of the first package, calling and executing first native code of the API to implement a function of a method of the class of the first package. The first native code is in a programming language different from the scripting language. The executing the first native code of the API includes calling a method of a class of the second package. The called method of the class of the second package is executed using a virtual machine of the scripting language. The application of the scripting language may be a Java card application, and the programming language may be a C programming language.

Abstract: A memory cell includes first, second, and third semiconductor regions laterally bounded by insulated conductive walls; a first insulating layer overlaying the first, second, and third semiconductor regions; and a second conductive layer disposed facing a part of each of first, second, and third semiconductor regions. A first top part of the first semiconductor region is first conductivity type doped and faces the second conductive layer. The second semiconductor region includes second top parts forming a transistor with the first insulating layer and second conductive layer. A third top part of the third semiconductor region is second conductivity type doped and faces the second conductive layer. To program the memory cell, an electrical field is applied between the first semiconductor region and the second conductive layer and electrical field is applied between the third semiconductor region and the second conductive layer.

Abstract: A body of laser direct structuring (LDS) encapsulating material encapsulates an integrated circuit device and an optical element mounted thereto. Laser activated trace regions and via openings at a first surface of the body are plated to form first conductive lines and first conductive vias. A first passivation layer covers the first conductive lines, the first surface of the body and a portion of the optical element. A second passivation layer covers a thinned backside of the body and integrated circuit device where distal ends of the first conductive vias are exposed. A redistribution layer (RDL) at the second passivation layer includes second conductive lines, pads, and second conductive vias which extend through the second passivation layer to electrically connect the second conductive lines to the distal ends of the first conductive vias. A solder mask layer on the second passivation layer includes openings at the pads of the RDL.

Abstract: A notification procedure is executed between an integrated circuit card operating in a communication device and a remote provisioning system. When the notification procedure is interrupted, the integrated circuit card is reset and a reset variable or flag is set. Notification information including a notification message, notification sequence number and a number of said one or more attempts left to perform for the notification procedure is stored in memory. After reset, the notification information is retrieved. If the reset variable or flag is set, the notification sequence number is maintained and a next attempt of the notification procedure is performed. If the reset variable or flag is not set, the notification sequence number is incremented. The reset variable or flag is reset when the notification procedure is completed.