Abstract: Integrated electronic device including: a semiconductor body of silicon delimited by a front surface and including at least a first semiconductive region of a first conductivity type, which extends into the semiconductor body starting from the front surface, and a second semiconductive region of a second conductivity type, which extends below the first semiconductive region; a dielectric capping region; a trench which extends through the dielectric capping region and through a front portion of the semiconductor body, in such a way that a part of the first semiconductive region laterally faces the trench, said trench partly extending inside the second semiconductive region; a conductive contact structure extending into the trench and including: a coating region of titanium silicide, which coats the bottom of the trench, in contact with the second semiconductive region, and also laterally coats the part of the first semiconductive region laterally facing the trench; and an inner conductive region.

Abstract: A bipolar transistor includes a first PN junction and a second PN junction. A first gate is located on the first PN junction. A second gate is located on the second PN junction.

Abstract: Microelectromechanical device comprising a supporting body, containing semiconductor material and a movable mass, constrained to the supporting body with a relative degree of freedom with respect to at least one motion direction, within a range of admissible positions. The device also comprises stopper elements, operable by the movable mass due to movements along the at least one motion direction and configured to apply stop forces to opposite sides of the movable mass, transversely to the at least one motion direction, when the movable mass reaches a respective endpoint of the range of admissible positions, so as to prevent the movable mass from exceeding the respective endpoint.

Abstract: The present disclosure relates to an avalanche photodiode pixel including: a transistor adapted to be controlled by an enable signal having a first state for controlling the enabling of the pixel and a second state for controlling the disabling of the pixel, the transistor being configured to couple an avalanche photodiode of the pixel to a node of application of a substrate voltage when the enable signal is in the first state; and an output circuit adapted to be controlled by the enable signal and configured to provide a pixel output signal when the enable signal is in the first state and to block the pixel output signal when the enable signal is in the second state.

Abstract: A device includes charge pumps, wherein each charge pump has an input receiving an input voltage, another input receiving a periodic control signal and an output delivering an output voltage. Each charge pump is selectively enabled or disabled. A first circuit delivers an error signal based on a difference between the output voltage and a reference voltage. A second circuit changes an operating parameter of the charge pumps on the basis of the error signal. A third circuit compares a current value of the operating parameter with two thresholds and, based on the result of the threshold comparisons, controls one of an increase in, a decrease in, and a retention of a number of enabled charge pumps.

Abstract: Provided is a circuit that sets a voltage of a failsafe node. The circuit includes a first voltage setting transistor configured to operate in a conductive state to set a voltage of the failsafe node to a supply voltage of a supply voltage node. The circuit includes first and second control transistors configured to control the first voltage setting transistor to operate in the conductive state in response to both the supply voltage and a pad node voltage of a pad node corresponding to logical one and control the first voltage setting transistor to operate in a nonconductive state in response to one of the supply voltage or the pad node voltage corresponding to the logical one and another one of the supply voltage or the pad node voltage corresponding to logical zero.

Abstract: An integrated circuit optical package includes a support substrate having a mounting face and an electrical interconnection network between the mounting face and contact pads located on a lower face of the support substrate. A cap includes a lateral wall fastened on the mounting face and an upper wall including a first opening. A first optical element is fastened on the upper wall of the cap to seal the first opening. An electromagnetic shielding element is embedded in the cap and configured to be coupled to a reference supply point via the interconnection network and at least one contact pad. A first electronic chip is mounted on the mounting face and in optical cooperation with the first optical element.

Abstract: A neural network includes an internal storage unit. The internal storage unit stores feature data received from a memory external to the neural network. The internal storage unit reads the feature data to a hardware accelerator of the neural network. The internal storage unit adapts a storage pattern of the feature data and a read pattern of the feature data to enhance the efficiency of the hardware accelerator.

Abstract: A neural network is able to reconfigure hardware accelerators on-the-fly without stopping downstream hardware accelerators. The neural network inserts a reconfiguration tag into the stream of feature data. If the reconfiguration tag matches an identification of a hardware accelerator, a reconfiguration process is initiated. Upstream hardware accelerators are paused while downstream hardware accelerators continue to operate. An epoch controller reconfigures the hardware accelerator via a bus. Normal operation of the neural network then resumes.

Abstract: A hybrid QFN package includes an encapsulant body that encapsulates a lead frame and integrated circuit (IC) device where the lead frame includes a die pad and vertically offset leads. Back sides of the die pad and encapsulant body are coplanar at first surface. Front sides of the leads, the IC device and the encapsulant body are substantially coplanar at a second surface. An insulating layer covers the second surface except at a portion of the leads located at the peripheral edge of the encapsulating body. Vias extend through the insulating layer to the leads and IC device. Wiring lines on the insulating layer interconnect the vias. A passivation layer covers the wiring lines and vias.

Abstract: A neural network includes an internal storage unit. The internal storage unit stores feature data received from a memory external to the neural network. The internal storage unit reads the feature data to a hardware accelerator of the neural network. The internal storage unit adapts a storage pattern of the feature data and a read pattern of the feature data to enhance the efficiency of the hardware accelerator.

Abstract: The present disclosure is directed to a device and method for human fall detection solution. Fall detection is performed by a low power inertial measurement unit (IMU) that is communicatively coupled between a pressure sensor and an application processor. The IMU includes one or more motions sensors, such as an accelerometer and gyroscope. The application processor is the main processor of the containing device. The IMU receives pressure sensor data from the pressure sensor, and executes the fall detection using both the pressure sensor data and accelerometer data.

Abstract: A sensor includes pixels supported by a substrate doped with a first conductivity type. Each pixel includes a portion of the substrate delimited by a vertical insulation structure with an image sensing assembly and a depth sensing assembly. The image sensing assembly includes a first region of the substrate more heavily doped with the first conductivity type and a first vertical transfer gate completely laterally surrounding the first region. Each of the depth sensing assemblies includes a second region of the substrate more heavily doped with the first conductivity type a second vertical transfer gate opposite a corresponding portion of the first vertical transfer gate. The second region is arranged between the second vertical transfer gate and the corresponding portion of the first vertical transfer gate.

Abstract: The present disclosure is directed to a device and method for accurately estimating a write self-time of a memory array. The write self-time is estimated by performing a simulated write operation on a write self-time bit cell having the same structure and arrangement as each of the bit cells of the memory array. The write operations on the bit cells of the memory array are stopped in response to detecting completion of the simulated write operation.

Abstract: An electronic device includes a memory and includes a plurality of word lines selectively driven by a decoder, with each pair of adjacent word lines having an underdrive circuit coupled therebetween. That underdrive circuit includes first and second transistors source/drain coupled in series with one another between the pair of adjacent word lines, the first and second transistors being replicas of a pull-down transistor and a pass gate transistor of bitcells the memory. One of the first and second transistors has its gate driven by a supply voltage and the other of the first and second transistor has its gate driven by a first read assist control signal.

Abstract: In an embodiment, a switching power supply includes: an output stage; a clock generator configured to generate a first clock signal; and a control circuit configured to control the output stage based on the first clock signal, wherein the switching power supply is configured to have a first operating mode synchronized by the first clock signal, and a second operating mode that is asynchronous, wherein the clock generator is configured to maintain the first clock signal at a constant value during the second operating mode.

Abstract: A method for testing a chip comprising receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.

Abstract: A convolutional accelerator framework (CAF) has a plurality of processing circuits including one or more convolution accelerators, a reconfigurable hardware buffer configurable to store data of a variable number of input data channels, and a stream switch coupled to the plurality of processing circuits. The reconfigurable hardware buffer has a memory and control circuitry. A number of the variable number of input data channels is associated with an execution epoch. The stream switch streams data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer during processing of the execution epoch. The control circuitry of the reconfigurable hardware buffer configures the memory to store data of the variable number of input data channels, the configuring including allocating a portion of the memory to each of the variable number of input data channels.

Abstract: Methods of operating an induction geyser include drawing current through a resonant tank via a transistor, generating a changing magnetic field around the resonant tank. Owing to the strategic placement of the resonant tank in proximity to a fluid tank, the changing magnetic field envelopes the fluid tank. In a first method, the voltage across the transistor's conduction terminals is monitored, and when this voltage surpasses a predefined threshold, indicating an overvoltage condition, a corrective action is initiated in which a gate driver pulls up a gate drive signal that drives the transistor. In a second method, the current flowing between the transistor's conduction terminals is monitored, and upon detecting an overcurrent condition where the current exceeds a set threshold the gate driver is activated to pull down the gate drive signal. Both methods aim to keep operation of the geyser within desired parameters.

Abstract: An electronic system includes a control circuit to provide a binary control signal alternating between a first binary state during first phases and a second binary state during second phases; a screen controlled by the control signal, the screen emitting light during each first phase, and to not emit any light during each second phase; a light sensor under the screen or along the edge of the screen, and providing a measurement signal representative of a quantity of light received by the sensor during a measurement phase or a plurality of consecutive measurement phases; and a synchronization device to synchronize each measurement phase with a second phase.