Patents Assigned to STMicroelectronics (Rousset) SAS
  • Patent number: 10540663
    Abstract: The authenticity of a product associated with a host device is verified through a process. The product contains, in segments of a non-volatile memory, several different functions stored in ciphered fashion. The process involves, in a first phase, the sending by the host device of a control signal for executing a function, with the product functioning to decipher the function and store the unciphered function in the non-volatile memory. The process further involves, in a second phase, the sending by the host device of a control signal for causing execution of the deciphered function, with the product functioning to execute the function and send a result of this execution back to the host device. The host device evaluates the received result to verify product authenticity.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: January 21, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Denis Farison, Fabrice Romain, Christophe Laurencin
  • Patent number: 10541270
    Abstract: The array of diodes comprises a matrix plane of diodes arranged according to columns in a first direction and according to rows in a second direction orthogonal to the first direction. The said diodes comprise a cathode region of a first type of conductivity and an anode region of a second type of conductivity, the said cathode and anode regions being superposed and disposed on an insulating layer situated on top of a semiconductor substrate.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: January 21, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Patent number: 10535672
    Abstract: A well of a first conductivity type is insulated from a substrate of the same first conductivity type by a structure of a triple well type. The structure includes a trench having an electrically conductive central part enclosed in an insulating sheath. The trench supports a first electrode of a decoupling capacitor, with a second electrode provided by the well.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: January 14, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Patent number: 10536836
    Abstract: A device, including a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: January 14, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics GmbH
    Inventors: Thierry Meziache, Pierre Rizzo, Alexandre Charles, Juergen Boehler
  • Patent number: 10530374
    Abstract: A method can be used for managing the operation of a phase-locked loop. The loop includes an oscillator voltage controlled by a control signal and a phase comparator receiving a reference signal and a feedback signal which arises from the output signal of the oscillator. The method includes a detection of a possible absence of transitions on the feedback signal for a first duration and, in response to such an absence, a forcing of the lowering of the voltage of the control signal at least until a reappearance of transitions on the feedback signal.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: January 7, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Bruno Gailhard
  • Patent number: 10522999
    Abstract: An integrated circuit includes a voltage regulating circuit in the form of only one transistor, or a group of several transistors in parallel, that are connected between first and second terminals configured to be coupled to an antenna. A control circuit operates to make the voltage regulating circuit inactive when a pulse generated by an electrostatic discharge event appears at one of the first and second terminals, regardless of the direction of flow of the pulse between the first and second terminals. An electrostatic discharge circuit is further provided to address the electrostatic discharge event.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: December 31, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Nicolas Demange
  • Publication number: 20190385957
    Abstract: An electronic integrated circuit chip includes a semiconductor substrate with a front side and a back side. A first reflective shield is positioned adjacent the front side of the semiconductor substrate and a second reflective shield is positioned adjacent the back side of the semiconductor substrate. Photons are emitted by a photon source to pass through the semiconductor substrate and bounce off the first and second reflective shields to reach a photon detector at the front side of the semiconductor substrate. The detected photons are processed in order to determine whether to issue an alert indicating the existence of an attack on the electronic integrated circuit chip.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 19, 2019
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Mathieu LISART, Bruce RAE
  • Patent number: 10511626
    Abstract: A method and associated circuits protect data stored in a secure data circuit of a telecommunication device equipped with a near-field communication (NFC) router, a microcontroller, and the secure data circuit. In the method, each message received with the NFC router is parsed to retrieve a communication pipe identifier and an instruction code. The communication pipe identifier and the instruction code are compared to corresponding information in a filter table. Instruction codes of particular messages that attempt to modify a communication pipe by reassigning one end of the communication pipe from the port of the NFC router to a different circuit are acted upon. These messages are blocked from reaching the secure data circuit when the instruction code is not authorized in the filter table, and these messages are permitted when the instruction code is authorized in the filter table.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: December 17, 2019
    Assignees: STMicroelectronics (Rousset) SAS, Proton World International N.V.
    Inventors: Thierry Huque, Olivier Van Nieuwenhuyze, Alexandre Charles
  • Patent number: 10510503
    Abstract: Methods of forming and operating a switching device are provided. The switching device is formed in an interconnect, the interconnect including a plurality of metallization levels, and has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: December 17, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christian Rivero, Pascal Fornara, Antonio di-Giacomo, Brice Arrazat
  • Patent number: 10502777
    Abstract: A method of testing a first circuit, including: a) applying a first signal between two terminals of the first circuit, the first circuit being powered off; and b) verifying that radio frequency waves transmitted by the first circuit correspond to an expected transmission.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: December 10, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Yann Bacher, Nicolas Froidevaux
  • Patent number: 10505592
    Abstract: A method of detection of the presence, by a first NFC device, of a second NFC device, during periodic field emission bursts, where detection thresholds are adjusted according to results obtained during one or a plurality of previous bursts.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: December 10, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Tramoni, Nicolas Cordier, Anthony Tornambe
  • Publication number: 20190371858
    Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 5, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Philippe BOIVIN, Jean-Jacques FAGOT
  • Publication number: 20190372537
    Abstract: An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 5, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Vincent BINET, Yohan JOLY
  • Patent number: 10497449
    Abstract: In an embodiment, a method is provided for controlling a level of a read current in a non-volatile memory that is powered by a supply voltage includes. A model current representative of an actual current able to flow during a readout through a read path of the memory is determined based on the value of the supply voltage. The model current is compared to a reference current having a reference value. A control signal is generated. The control signal is to control the generation of the read current having a level equal to the lowest value between a fraction of the value of the model current and the reference value.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 3, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Fran├žois Tailliet
  • Patent number: 10490632
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: November 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • Publication number: 20190355674
    Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 21, 2019
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Denis FARISON, Romain COFFY, Jean-Michel RIVIERE
  • Publication number: 20190354728
    Abstract: The supply voltage for a module of an integrated circuit managed to support protection against side channel attacks. Upon startup of the integrated circuit, one action from the following actions is selected in response to a command: supplying the module with the supply voltage having a fixed value that is selected from a plurality of predetermined values, or varying the value of the supply voltage in time with a pulsed signal.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 21, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Thomas ORDAS, Yanis LINGE, Jimmy FORT
  • Patent number: 10482957
    Abstract: The disclosure relates to a memory cell comprising a resistive RAM memory element and a selection transistor, in which the memory element is positioned on a flank of the selection transistor.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: November 19, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Philippe Boivin, Simon Jeannot, Olivier Weber
  • Patent number: 10475713
    Abstract: An integrated circuit includes several metallization levels separated by an insulating region. A hollow housing whose walls comprise metallic portions is produced within various metallization levels. A controllable capacitive device includes a suspended metallic structure situated in the hollow housing within a first metallization level including a first element fixed on two fixing zones of the housing and at least one second element extending in cantilever fashion from the first element and includes a first electrode of the capacitive device. A second electrode includes a first fixed body situated at a second metallization level adjacent to the first metallization level facing the first electrode. The first element is controllable in flexion from a control zone of this first element so as to modify the distance between the two electrodes.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: November 12, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 10473709
    Abstract: An integrated circuit chip stack includes a main integrated circuit chip and at least one auxiliary integrated circuit chip. The main integrated circuit chip contains circuit components to be protected. The auxiliary integrated circuit chip is mounted to a surface of the main integrated circuit chip and includes a metal plane connected to ground located opposite the circuit components to be protected. The auxiliary integrated circuit chip further includes at least one insulated conductive track forming a tight pattern opposite the circuit components to be protected. A detection circuit is connected to the at least one conductive track and is configured to detect interruption of the at least one insulated conductive track.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: November 12, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas