Patents Assigned to STMicroelectronics (Rousset) SAS
  • Publication number: 20220148962
    Abstract: An electronic chip includes a shared strip with first and second spaced apart portions extending along a direction of elongation and an intermediate connecting portion extending between the first and second portions. The second portion is connected to a pad that has a greater surface area than the second portion. The first portion is formed by a first plurality of metallic strips. Metallic strips of the first plurality of metallic strips that are adjacent and side by side are separated by a distance smaller than a width of those metallic strips. The second portion is formed by a second plurality of metallic strips. Metallic strips of the second plurality of metallic strips that are adjacent and side by side are separated by a distance smaller than a width of those metallic strips.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 12, 2022
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Samuel BOSCHER, Yann REBOURS, Michel CUENCA
  • Patent number: 11329067
    Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 10, 2022
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Jean-Jacques Fagot, Philippe Boivin, Franck Arnaud
  • Patent number: 11329011
    Abstract: An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: May 10, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Patent number: 11329796
    Abstract: A calculation is performed on a first number and a second number. For each bit of the second number a first function is performed. The first function inputs include contents of a first register, contents of a second register and the first number. A result of the first function is placed in a third register. For each bit of the second number, a second function is performed which has as inputs contents of the third register and the contents of a selected one of the first and the second register according to a state of a current bit of the second number. A result of the second function is stored in the selected one of the first and second register.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: May 10, 2022
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Ibrahima Diop, Yanis Linge
  • Patent number: 11328098
    Abstract: An electronic circuit includes an interface, a read-only memory in which encrypted data are stored, and cryptographic circuitry coupled to the interface. In operation, the cryptographic circuitry uses a decryption key received via the interface to decrypt the encrypted data. The electronic circuit performs one or more operations using the decrypted data.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: May 10, 2022
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Fabrice Marinet
  • Publication number: 20220139782
    Abstract: An integrated circuit includes metal-oxide-semiconductor “MOS” transistors formed on a semiconductor substrate. The MOS transistors have gate stacks belonging to at least one gate stack category and dielectric regions of sidewall spacers on the sides of the gate stacks. At least a first MOS transistor has a gate stack of said at least one gate stack category that includes dielectric regions of sidewall spacers having a first width. At least a second MOS transistor has a gate stack of the same gate stack category with dielectric regions of sidewall spacers having a second width different from the first width.
    Type: Application
    Filed: November 2, 2021
    Publication date: May 5, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Franck JULIEN
  • Publication number: 20220140232
    Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.
    Type: Application
    Filed: October 21, 2021
    Publication date: May 5, 2022
    Applicants: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Philippe BOIVIN, Roberto SIMOLA, Yohann MOUSTAPHA-RABAULT
  • Publication number: 20220139899
    Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.
    Type: Application
    Filed: November 2, 2021
    Publication date: May 5, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal FORNARA, Roberto SIMOLA
  • Publication number: 20220140233
    Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.
    Type: Application
    Filed: October 22, 2021
    Publication date: May 5, 2022
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Philippe BOIVIN
  • Patent number: 11321270
    Abstract: A method for encoding a data value to be transmitted on an SPI serial bus includes an operation to modify a status register of a memory, at least at one chosen time instant, as a function of all or part of the data value to be transmitted.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • Patent number: 11322503
    Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Publication number: 20220130904
    Abstract: The present description concerns a method of forming a track in a first layer, including a) forming a cavity in the first layer; b) totally filling the cavity with a first material; and c) partially removing the first material from the upper portion of the cavity, to form the track made of the first material.
    Type: Application
    Filed: October 21, 2021
    Publication date: April 28, 2022
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Philippe BOIVIN
  • Publication number: 20220123119
    Abstract: A memory transistor for a non-volatile memory cell includes a source region and a drain region implanted in a semiconductor substrate. The source region is spaced from the drain region. A double gate region for the memory transistor extends at least partly in depth in the semiconductor substrate between the source region and the drain region and further extends beyond this source region and this drain region. The memory cell further includes a selection transistor having a gate region that partially extends over the double gate region for the memory transistor.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian RIVERO, Philippe BOIVIN, Francois TAILLIET, Roberto SIMOLA
  • Publication number: 20220120589
    Abstract: An integrated circuit includes a first substrate. A MOS transistor has a first polysilicon region electrically isolated from the first substrate and including a gate region. A second polysilicon region is electrically isolated from the first polysilicon region and from the first substrate. The second polysilicon region includes a source region, a substrate region and a drain region of the MOS transistor. The first polysilicon region is located between an area of the first substrate and the second polysilicon region.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Pascal FORNARA
  • Publication number: 20220122910
    Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.
    Type: Application
    Filed: December 30, 2021
    Publication date: April 21, 2022
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François TAILLIET, Guilhem BOUTON
  • Publication number: 20220115441
    Abstract: The disclosure relates to integrated circuits including one or more rows of transistors and methods of forming rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a first semiconductor layer having a plurality of first conduction regions, a second semiconductor layer having a second conduction region, a common base between the first semiconductor layer and the second semiconductor layer, and a plurality of insulator walls extending in a first direction. The first conduction regions are separated from one another by the insulator walls. The integrated circuit further includes an insulating trench extending in a second direction and in contact with each of the bipolar transistors of the row of bipolar transistors. A conductive layer is coupled to the base, and the conductive layer extends through the insulator walls and extends at least partially into the insulating trench.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Philippe BOIVIN
  • Patent number: 11300606
    Abstract: An electronic assembly includes a board and a system mounted to the board. The system includes an impedance matching circuit coupled to a contactless component. A detection circuit operates to carrying out a process for detecting on the board of potential faults in the system mounted to the board. The detection circuit includes a circuit incorporated into the contactless component itself and configured to carrying out a first part of the process for detecting. A processing circuit of the detection circuit performs a second part of the process for detecting based on results of the first part.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: April 12, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Nicolas Cordier
  • Patent number: 11300985
    Abstract: A device includes a current source, a first transistor connected between a first supply rail and an output terminal, and a second transistor connected between the output terminal and a first terminal of the current source, wherein a second terminal of the current source is connected to a second supply rail. A variable-gain amplifier circuit responds to a potential at the first terminal of the current source by applying a potential to the control terminal of the first transistor. A gain of the amplifier circuit is determined by a potential at the output terminal.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: April 12, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Jimmy Fort
  • Patent number: 11303118
    Abstract: The present disclosure relates to a device including a rectifying bridge including: a branch connected between first and second nodes; another branch including first and second MOS transistors series-connected between the first and second nodes and having their sources coupled together; a resistor connecting the gate of the first transistor to the second node; another resistor connecting the gate of the second transistor and the first node; and for each transistor, a circuit including first and second terminals respectively connected to the drain and to the gate of the transistor, and being configured to electrically couple its first and second terminals when a voltage between the first terminal of the circuit and the first terminal of the other circuit is greater than a threshold of the circuit.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: April 12, 2022
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: François Tailliet
  • Publication number: 20220107356
    Abstract: A test circuit and a method for testing an integrated circuit are provided. The integrated circuit includes a test circuit. The test circuit includes a conductive track extending over at least a portion of the periphery of the integrated circuit, at least one component and an activation circuit adapted to deviating an input data signal into the conductive track during a test mode, and to transmitting the input data signal to the at least one component during a normal operating mode.
    Type: Application
    Filed: September 7, 2021
    Publication date: April 7, 2022
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Francois TAILLIET