Patents Assigned to STMicroelectronics (Rousset) SAS
  • Publication number: 20210103788
    Abstract: A first element and a second element of a same device communicate with each other. The first element sends the second element a first piece of information representative of energy supplied by an electromagnetic field supplying power the device. The second element adapts its operating frequency as a function of the first piece of information.
    Type: Application
    Filed: September 22, 2020
    Publication date: April 8, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Julien MERCIER
  • Patent number: 10971633
    Abstract: In accordance with an embodiment of the present invention, a method of making a semiconductor device includes simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, where the semiconductor layer has a first conductivity type. The method further includes etching through first openings of a mask layer to form first implantation surfaces on the semiconductor layer and to form a plurality of projecting regions including conductive material of the conductive layer over the semiconductor layer. The method further includes using the plurality of projecting regions as a part of a first implantation mask, performing a first implantation of dopants having a second conductivity type into the semiconductor layer, to form a sequence of PN junctions forming diodes in the semiconductor layer. The diodes vertically extend from an upper surface of the semiconductor layer to the insulating layer.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: April 6, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Patent number: 10971578
    Abstract: The disclosure concerns a capacitive component including a trench and, vertically in line with the trench, first portions of a first silicon oxide layer and first portions of second and third conductive layers including polysilicon or amorphous silicon, the first portion of the first layer being between and in contact with the first portions of the second and third layers.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: April 6, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak Marzaki, Pascal Fornara
  • Publication number: 20210091015
    Abstract: An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal FORNARA, Fabrice MARINET
  • Patent number: 10955898
    Abstract: An electronic device includes an appended module coupled to a core having a standby state comprising a first power supply circuit, a first clock and a circuit that recognizes multiple vocal commands timed by the first clock. The appended module includes a second power supply circuit independent of the first power supply circuit, a second clock independent of the first clock and having a frequency lower than that of the first clock, digital unit timed by the second clock including a sound capture circuit that delivers a processed sound signal, and a processing unit configured in order, in the presence of a parameter of the processed sound signal greater than a threshold, to analyze the content of the processed sound signal and to deliver, when the content of the sound signal comprises a reference pattern, an activating signal to the core that can take it out of its standby state.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: March 23, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jonathan Cottinet, Jean Claude Bini
  • Patent number: 10958150
    Abstract: An electronic circuit includes a switched-mode power supply and a linear voltage regulation circuit having an input stage, a first output stage, and a second output stage. A first load is capable of being powered either by the switched-mode power supply in series with the regulation circuit or by the regulation circuit without the switched-mode power supply.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 23, 2021
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Michel Cuenca, Bruno Gailhard, Daniele Mangano
  • Patent number: 10949572
    Abstract: The supply voltage for a module of an integrated circuit managed to support protection against side channel attacks. Upon startup of the integrated circuit, one action from the following actions is selected in response to a command: supplying the module with the supply voltage having a fixed value that is selected from a plurality of predetermined values, or varying the value of the supply voltage in time with a pulsed signal.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: March 16, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas, Yanis Linge, Jimmy Fort
  • Patent number: 10950559
    Abstract: An electronic integrated circuit chip includes a semiconductor substrate with a front side and a back side. A first reflective shield is positioned adjacent the front side of the semiconductor substrate and a second reflective shield is positioned adjacent the back side of the semiconductor substrate. Photons are emitted by a photon source to pass through the semiconductor substrate and bounce off the first and second reflective shields to reach a photon detector at the front side of the semiconductor substrate. The detected photons are processed in order to determine whether to issue an alert indicating the existence of an attack on the electronic integrated circuit chip.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: March 16, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Mathieu Lisart, Bruce Rae
  • Patent number: 10943862
    Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: March 9, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Abderrezak Marzaki, Arnaud Regnier, Stephan Niel
  • Patent number: 10943876
    Abstract: An attack on an integrated circuit using a beam of electrically charged particles is detected by collecting charges due to the attack using at least one electrically conductive body that is electrically coupled to the floating gate of a state transistor. Prior to the attack, the state transistor is configured to confer an initial threshold voltage. The collected charges passed to the floating gate cause a modification of the threshold voltage of the state transistor. Detection of the attack is made by determining that the threshold voltage of the state transistor is different from the initial threshold voltage.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: March 9, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fabrice Marinet, Pascal Fornara
  • Patent number: 10943973
    Abstract: A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: March 9, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Publication number: 20210065834
    Abstract: A method for detecting a writing error of a datum in memory includes: storing at least two parts of equal size of a binary word representative of said datum at the same address in at least two identical memory circuits, and comparing internal control signals of the two memory circuits to determine existence of the writing error.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 4, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Fabrice ROMAIN, Mathieu LISART
  • Publication number: 20210067177
    Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 4, 2021
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Alps) SAS
    Inventors: Fabrice ROMAIN, Mathieu LISART, Patrick Arnould
  • Patent number: 10938107
    Abstract: A circuit for driving an antenna of near field communication (NFC) device, includes: a first variable resistor coupled to a first terminal of the antenna via a first capacitor; a second variable resistor coupled to a second terminal of the antenna via a second capacitor; and a control circuit configured to cause the first variable resistor and the second variable resistor to each have a selected one of a first resistance level, a second resistance level, and a third resistance level based on an operating phase of the circuit.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 2, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Nicolas Cordier
  • Patent number: 10937746
    Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunneling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: March 2, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak Marzaki, Pascal Fornara
  • Publication number: 20210057358
    Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed to detect a DFA attack by fault injection into the integrated circuit.
    Type: Application
    Filed: November 6, 2020
    Publication date: February 25, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Abderrezak MARZAKI
  • Publication number: 20210057329
    Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.
    Type: Application
    Filed: August 21, 2019
    Publication date: February 25, 2021
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Abderrezak MARZAKI, Arnaud REGNIER, Stephan NIEL
  • Patent number: 10930351
    Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 23, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Julien Delalleau
  • Patent number: 10930757
    Abstract: A method of manufacturing a MOS transistor includes forming a conductive first gate and forming insulating spacers along opposite sides of the gate, wherein the spacers are formed before the gate.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 23, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Arnaud Regnier, Dann Morillon, Franck Julien, Marjorie Hesse
  • Patent number: 10931519
    Abstract: A method for configuring a first device for a near-field communication with a second device, wherein a peer-to-peer mode is selected if the second device draws the power supply of its circuits from a battery.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: February 23, 2021
    Assignees: PROTON WORLD INTERNATIONAL N.V., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Olivier Van Nieuwenhuyze, Alexandre Charles