Abstract: A method is presented for monitoring a tampering state of closed container wherein a first electrically conductive wire extends across a slot between two portions of the closed container. The method includes applying a voltage across the first electrically conductive wire, sensing a voltage at one end of the first electrically conductive wire, and generating a signal indicating the tampering state of the closed container in response to the sensed voltage. The sensed voltage has a first voltage value if the first electrically conductive wire has been severed by tampering, and this tampered state is then reported using near field communication. The near field communication is blocked if it is sensed that the severed first electrically conductive wire has been repaired.

Abstract: A transistor includes a source region, a drain region and a body region arranged in a semiconductor layer. A gate region tops the body region. The body region includes a first doped layer and a second layer between the first doped layer and the gate region. The second layer is an epitaxial layer that is less heavily doped than the first doped layer.

Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

Abstract: The present disclosure concerns a voltage regulation circuit formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising: between a first terminal and a second terminal, a first resistor and a first d-mode type HEMT transistor; and between the first terminal and the third terminal, a second d-mode type HEMT transistor; wherein the midpoint between the first resistor and the first transistor is coupled to the gates of the first and second transistors.

Abstract: A device includes a memory and cryptographic processing circuitry coupled to the memory. The memory, in operation, stores one or more lookup tables. The cryptographic processing circuitry, in operation, processes masked data and protects the processing of masked data against side channel attacks. The protecting includes applying masked binary logic operations to masked data using lookup tables of the one or more lookup tables.

Abstract: The present disclosure concerns overtemperature protection circuit formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising: a first resistor having a first positive temperature coefficient and being arranged in said gallium nitride layer; and a second resistor having a second temperature coefficient different from the first coefficient.

Abstract: The present disclosure concerns a driver of a first e-mode type HEMT power transistor adapted to receiving a maximum voltage of 650 V between its drain and its source, the circuit being formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, and comprising at least a second e-mode type transistor adapted to directly transmitting a control voltage to the gate of the first transistor and having an area greater than 5 mm2.

Abstract: The present disclosure concerns an electronic device formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising at least one e-mode type HEMT power transistor adapted to receiving a maximum voltage of 650 V between its drain and its source, and an analog circuit for controlling said power transistor.

Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator including first and second inputs. The first input is configured to receive, during a first phase, a first voltage ramp and, during a second phase, a set point voltage. The second input is configured to receive, during the first phase, the set point voltage and, during the second phase, a second voltage ramp.

Abstract: A method and associated circuits protect data stored in a secure data circuit of a telecommunication device equipped with a near-field communication (NFC) router, a microcontroller, and the secure data circuit. In the method, each message received with the NFC router is parsed to retrieve a communication pipe identifier and an instruction code. The communication pipe identifier and the instruction code are compared to corresponding information in a filter table. Instruction codes of particular messages that attempt to modify a communication pipe by reassigning one end of the communication pipe from the port of the NFC router to a different circuit are acted upon. These messages are blocked from reaching the secure data circuit when the instruction code is not authorized in the filter table, and these messages are permitted when the instruction code is authorized in the filter table.

Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

Abstract: A connector that is configured to receive a smart card includes: a first contact configured to receive a power supply voltage and corresponding to a first (power supply) contact area of the smart card, a second contact configured to receive a reference voltage and corresponding to contact a second (reference voltage) contact area of the smart card, and a third contact corresponding to a three-state (input/output) contact area of the smart card. A first light-emitting diode having an anode coupled to the third contact and a cathode coupled to the second contact. A second light-emitting diode has a cathode coupled to the third contact and an anode coupled to the first contact. Turning on/off of the first and second light-emitting diode is controlled by the smart card through the signal at the three-state (input/output) contact area.

Abstract: A contactless device includes an impedance matching and filter circuit connected to an antenna and being on the one hand operable for contactlessly communicating with a second device via the antenna, and on the other hand operable for contactlessly charging a rechargeable power supply of a third device via the antenna. A method of control includes modifying the impedance matching and filter circuit of the contactless device depending on whether the contactless device carries out the contactless communication or carries out the contactless charging.

Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.

Abstract: In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

Abstract: The present disclosure relates to a method for aligning a smartphone providing NFC wireless power for charging a battery of a device, the method comprising: emitting, with a first NFC antenna of the smartphone, an NFC field for wirelessly charging the battery of the device comprising a second NFC antenna; obtaining, with the smartphone, a measured value of a signal representative of the NFC field strength between the smartphone and the device; determining, by the smartphone, a range of values of a plurality of ranges of values the measured value belongs; and emitting, by the smartphone, at least one notification signal to a user with a frequency determined by the determined range of values.

Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed to detect a DFA attack by fault injection into the integrated circuit.

Abstract: A method of pairing between a first host device and a first peripheral device includes entering by a user of the first host device a verification value, as well as comparing, by the first peripheral device, between the verification value and a first secret value stored in a memory of the first peripheral device. When the verification corresponds to the first secret value, the method of pairing further includes calculating and storing a first pairing key by the first host device and the first peripheral device to perform the pairing.

Abstract: Data exchanges between an ultra-wide band communication module and a secure element are controlled such that the data exchanges pass through a near-field communication router. The near-field communication router controls routing of the data exchanges so that the data exchanges do not pass through a host circuit that is also coupled to the near-field communication router.