Abstract: The present description concerns a ROM including at least one first rewritable memory cell.

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

Abstract: An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node.

Abstract: The present description concerns an electrostatic discharge protection device including a first clipping circuit coupled between a first node and a second node and a second active clipping circuit, series-coupled with a first resistor, the second clipping circuit and the first resistor being coupled between the first and second nodes, the second clipping circuit including a field-effect transistor having a metal-oxide-semiconductor structure.

Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

Abstract: A light-emitting diode has an anode terminal coupled to a node of application of a power supply voltage by a first transistor and a cathode terminal coupled to a node of application of a reference voltage by a second transistor. A microcontroller includes a digital-to-analog converter and a comparator, with the comparator having a first input coupled to one of the anode and cathode terminals of the diode and a second input configured to receive an output voltage of the converter. An output signal of the comparator controls one of the first and second transistors to turn off when the comparator detects an operating condition where current flow in the light-emitting diode exceeds maximum current limit (such as with the light-emitting diode operating in an exponential operating area.

Abstract: A physically unclonable function device includes a set of diode-connected MOS transistors having a random distribution of respective threshold voltages. A first circuit is configured to impose, on each first transistor, a fixed respective gate voltage regardless of the value of a current flowing in this first transistor. A second circuit is configured to impose, on each second transistor, a fixed respective gate voltage regardless of the value of a current flowing in this second transistor. A current mirror stage is coupled between the first circuit and the second circuit and is configured to deliver the reference current from a sum of the currents flowing in the first transistors. A comparator is configured to deliver a signal whose level depends on a comparison between a first current obtained from a reference current based on the first transistors and a second current of the second transistors.

Abstract: A method of configuring a contactless communication device is provided. The contactless communication device includes integrated circuits hosting at least two applications compatible with different communication protocols or the same communication protocol and using different communication parameters and a contactless communication circuit. The method includes stopping, by the contactless communication circuit, the transmission of answers of the contactless communication device to requests transmitted by a proximity coupling reader during a transaction initiated by the reader to cause the initiation by the reader of a new transaction.

Abstract: A circuit for a communication device and a method for switching a communication device are disclosed. In an embodiment, a method includes activating at least one first antenna and at least one second antenna of a near-field communication (NFC) device for switching the NFC device between first field detection phases and second card detection phases.

Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.

Abstract: The system on a chip includes at least a first digital domain configured to be reinitialized by a first reinitialization signal, a second digital domain and an interface circuit. The interface circuit includes a starting register in the first digital domain, a destination register in the second digital domain and a synchronization circuit in the first digital domain. The interface circuit is configured to transfer data from the starting register to the destination register upon command of a control signal transmitted by the synchronization circuit. The starting register and the synchronization circuit are configured to not be reinitialized by the first reinitialization signal.

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

Abstract: A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.

Abstract: A switched-mode power supply includes a voltage ramp generation circuit that generates a voltage ramp signal. The voltage ramp generation circuit includes, selectively connected in parallel, at least three capacitors. The selective connection of the capacitors is made according to a value of an internal power supply voltage of the switched-mode power supply.

Abstract: In an embodiment, a device includes a switching power supply configured to have a first operating mode synchronized by a first clock signal generated by a clock generator a second asynchronous operating mode. The clock generator is configured such that the first clock signal becomes equal, upon transition from the second operating mode to the first operating mode, to the signal having the closest rising edge of a second clock signal and a third clock signal complementary to the second clock signal.

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

Abstract: A first input node receives a first input signal and a second input node receives a second input signal. The first and second input signals are in phase quadrature. An edge detector circuit senses the first input signal and produces a pulsed signal indicative of edges detected in the first input signal. A pulse skip and reset circuit senses the pulsed signal and the second input signal, and produces a reset signal indicative of pulses detected in the pulsed signal while the second input signal is de-asserted. A sampling circuit senses the second input signal and the reset signal, and produces an output signal that is deasserted in response to assertion of the second input signal and is asserted in response to a pulse being detected in the reset signal.

Abstract: An embodiment method for smoothing consumed current is based on a current copying suite and on a current source supplying a reference current, the currents being transformed into a reference voltage for the regulation of a voltage regulator such that the consumed current viewed by the power supply only depends on the reference current.

Abstract: The integrated circuit comprises at least one transistor including a separate gate structure and field plate, disposed on a front face of a semiconductor substrate, and a doped conduction region in the semiconductor substrate located plumb with an edge of the gate structure and plumb with an edge of the field plate.