Patents Assigned to STMICROELECTRONICS (ROUSSET)
  • Ring oscillator operation management method and apparatus
    Patent number: 10218336
    Abstract: A device and method can be used to manage the operation of a ring oscillator circuit. A master oscillator circuit generates a master supply voltage. The master supply voltage associated with a stable oscillation rate of the master oscillator circuit. The master oscillator circuit is supplied with current and is structurally identical to the ring oscillator circuit. A capacitive circuit is loaded with a load voltage originating from the master supply voltage. In response to a control signal, the ring oscillator circuit is supplied with a current controlled by a voltage delivered by the capacitive circuit, in such a way as to provide a stable oscillation rate for the ring oscillator circuit.
    Type: Grant
    Filed: February 19, 2017
    Date of Patent: February 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • CO-INTEGRATION OF BULK AND SOI TRANSISTORS
    Publication number: 20190057981
    Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
    Type: Application
    Filed: August 7, 2018
    Publication date: February 21, 2019
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Jacques FAGOT, Philippe BOIVIN, Franck ARNAUD
  • DPA protection of a rijndael algorithm
    Patent number: 10210776
    Abstract: A method of protecting a Rijndael-type algorithm executed by an electronic circuit against side channel attacks, wherein: each block of data to be encrypted or to be decrypted is masked with a first mask before a non-linear block substitution operation is applied based on a substitution box, and is then unmasked with a second mask after the substitution; and the substitution box is recalculated, block by block, before the non-linear operation is applied, the processing order of the blocks of the substitution box being submitted to a random permutation, commutative with the non-linear substitution operation.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Nicolas Bruneau
  • Verification of the sensitivity of an electronic circuit executing a modular exponentiation calculation
    Patent number: 10209961
    Abstract: A method of verifying the sensitivity of an electronic circuit executing a modular exponentiation calculation in a first register and a second register, successively including, for each bit of the exponent: a first step of multiplying the content of one of the registers, selected from among the first register and the second register according to the state of the bit of the exponent, by the content of the other one of the first and second registers, placing the result in said one of the registers; a second step of squaring the content of said other one of the registers by placing the result in this other register, wherein the content of that of the first and second registers which contains the multiplier of the operation of the first step is disturbed, for each bit of the exponent, during the execution of the first step.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: February 19, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Yannick Teglia
  • System and method for adjusting EEPROM write cycle duration according to supply voltage variation
    Patent number: 10210933
    Abstract: A method of controlling a cycle for writing at least one data item to at least one memory slot of the electrically programmable and erasable read-only memory type disposed in an electronic circuit supplied by a supply voltage includes a controlled increase of the duration of the write cycle in the presence of a decrease in the supply voltage.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: February 19, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francois Tailliet, Marc Battista
  • Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
    Patent number: 10211291
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • Receiver and method for processing a signal coming from a transmission channel
    Patent number: 10211884
    Abstract: A method is for processing a channel analog signal coming from a transmission channel. The method may include converting the channel analog signal into a channel digital signal, and detecting a state of the transmission channel based on the channel digital signal to detect whether the transmission channel is, over an interval of time, one or more of linear and time invariant and linear and cyclostationary.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yoann Bouvet, Pierre Demaj
  • METHOD FOR DETECTING THINNING OF THE SUBSTRATE OF AN INTEGRATED CIRCUIT FROM ITS BACK SIDE, AND ASSOCIATED INTEGRATED CIRCUIT
    Publication number: 20190043814
    Abstract: An integrated electronic circuit includes a semiconductor substrate with a semiconductor well that is isolated by a buried semiconductor region located under the semiconductor well. A vertical MOS transistor formed in the semiconductor well includes a source-drain region provided by the buried semiconductor region. Backside thinning of the semiconductor substrate is detected by biasing the vertical MOS transistor into an on condition to supply a current and then comparing that current to a threshold. Current less than a threshold is indicative that the semiconductor substrate has been thinned from the backside.
    Type: Application
    Filed: August 1, 2018
    Publication date: February 7, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak MARZAKI, Christian RIVERO, Quentin HUBERT
  • Stucture for protecting an integrated circuit against electrostatic discharges
    Patent number: 10199368
    Abstract: An integrated circuit includes at least one input-output pad and a terminal intended to be connected to a source of a reference potential and further including a protection structure including a thyristor forward-connected between the pad and the terminal. The thyristor includes a first resistor between its cathode gate and the terminal. At least one Zener diode is disposed between the thyristor and the pad. The anode of the Zener diode is connected to the cathode gate of the thyristor and the cathode of the Zener diode is connected to the pad via at least one second resistor. The junction of the Zener diode is different from the junctions of the PNPN structure of the thyristor.
    Type: Grant
    Filed: February 19, 2017
    Date of Patent: February 5, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Device and method for managing the current consumption of an integrated module
    Patent number: 10198683
    Abstract: An electronic device randomly modifies a current profile of a logic circuit by using an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 5, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas, Yanis Linge, Jimmy Fort
  • Vertical memory cell with non-self-aligned floating drain-source implant
    Patent number: 10192999
    Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 29, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Marc Mantelli, Stephan Niel, Arnaud Regnier, Francesco La Rosa, Julien Delalleau
  • INTEGRATED CIRCUIT WITH DETECTION OF THINNING VIA THE BACK FACE AND DECOUPLING CAPACITORS
    Publication number: 20190027448
    Abstract: A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A device is configured to detect a thinning of the semiconductor substrate from the back face. The device includes at least one trench that extends within the semiconductor well between two peripheral locations from the front face down to a location situated at a distance from a bottom of the semiconductor well. The trench is electrically isolated from the semiconductor well. A detection circuit is configured to measure a physical quantity representative of well electrical resistance between two contact areas respectively situated on either side of the at least one first trench.
    Type: Application
    Filed: September 24, 2018
    Publication date: January 24, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • INTEGRATED CIRCUIT CONTAINING A DECOY STRUCTURE
    Publication number: 20190027447
    Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.
    Type: Application
    Filed: July 16, 2018
    Publication date: January 24, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Julien DELALLEAU, Christian RIVERO
  • TRANSISTOR COMPRISING A LENGTHENED GATE
    Publication number: 20190027581
    Abstract: A MOS transistor is produced on and in an active zone and included a source region and a drain region. The active zone has a width measured transversely to a source-drain direction. A conductive gate region of the MOS transistor includes a central zone and, at a foot of the central zone, at least one stair that extends beyond the central zone along at least an entirety of the width of the active zone.
    Type: Application
    Filed: July 16, 2018
    Publication date: January 24, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Julien DELALLEAU, Christian RIVERO
  • DOUBLE-GATE MOS TRANSISTOR WITH INCREASED BREAKDOWN VOLTAGE
    Publication number: 20190027566
    Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.
    Type: Application
    Filed: July 16, 2018
    Publication date: January 24, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian RIVERO, Julien DELALLEAU
  • INTEGRATED CIRCUIT HAVING A HIDDEN SHARED CONTACT
    Publication number: 20190027439
    Abstract: An integrated circuit includes a substrate and an interconnect. A substrate zone is delineated by an insulating zone. A polysilicon region extends on the insulating zone and includes a strip part. An isolating region is situated between the substrate and the interconnect and covers the substrate zone and the polysilicon region. A first electrically conductive pad passes through the isolating region and has a first end in electrical contact with both the strip part and the substrate zone. A second end of the electrically conductive pad is in electrical contact with the interconnect. A second electrically conductive pad also passes through the isolating region to make electrical contact with another region. The first and second electrically conductive pads have equal or substantially equal cross sectional sizes, within a tolerance.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 24, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Julien DELALLEAU, Christian RIVERO
  • MOS TRANSISTOR WITH REDUCED HUMP EFFECT
    Publication number: 20190027565
    Abstract: A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 24, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian RIVERO, Guilhem BOUTON, Pascal FORNARA, Julien DELALLEAU
  • Configurable delay line
    Patent number: 10187040
    Abstract: A delaying element includes a first XOR logic gate and a second XOR logic gate. A first input of the first XOR logic gate defines an input terminal. A first input of the second XOR logic gate is connected to an output of the first XOR logic gate. An output of the second XOR logic gate defines an output terminal. The second inputs of the first and second XOR logic gates are connected to a second input terminal.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: January 22, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Albert Martinez
  • Integrated circuit chip reinforced against front side deprocessing attacks
    Patent number: 10186491
    Abstract: An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the stack. A material at least partially fills the cavity. The fill material has a selectivity to polishing and/or to etching different by more than 10% from a selectivity to polishing and/or to etching of a material forming an insulator of the interconnection stack.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: January 22, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Sébastien Petitdidier, Mathieu Lisart
  • Circuit and method for activating an NFC device
    Patent number: 10187116
    Abstract: An embodiment near-field communication (NFC) router, includes a first switch coupled between a first terminal of the NFC router and a second terminal of the NFC router; and a rectifier bridge having an output terminal coupled to a control terminal of the first switch, the rectifier bridge being configured to rectify a signal detected by an antenna external to the NFC router.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: January 22, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Nathalie Vallespin