Patents Assigned to STMICROELECTRONICS (ROUSSET)
  • Backside fib probing detector in a forward and reverse body biasing architecture
    Patent number: 9935062
    Abstract: An integrated circuit including a plurality of first semiconductor strips of a first conductivity type and of second semiconductor strips of a second conductivity type arranged in alternated and contiguous fashion on a region of the second conductivity type, including for each of the first strips: a plurality of bias contacts; for each bias contact, a switch capable of applying a potential on the bias contact; two detection contacts arranged at the ends of the first strip; and a detection circuit having its activation causing the turning off of the switches and the comparison with a threshold of the resistance between the detection contacts.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: April 3, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Mathieu Lisart, Nicolas Borrel
  • Method of forming MOS and bipolar transistors
    Patent number: 9929146
    Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: March 27, 2018
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Olivier Weber, Emmanuel Richard, Philippe Boivin
  • Compact non-volatile memory device
    Patent number: 9922712
    Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.
    Type: Grant
    Filed: February 19, 2017
    Date of Patent: March 20, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Julien Delalleau
  • METHOD FOR PRODUCING TRANSISTORS, IN PARTICULAR SELECTION TRANSISTORS FOR NON-VOLATILE MEMORY, AND CORRESPONDING DEVICE
    Publication number: 20180076265
    Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.
    Type: Application
    Filed: February 20, 2017
    Publication date: March 15, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Philippe Boivin, Jean-Jacques Fagot
  • Method for detecting a thinning of the semiconductor substrate of an integrated circuit from its back face and corresponding integrated circuit
    Patent number: 9916902
    Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: March 13, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • METHOD OF PROCESSING SIGNALS, IN PARTICULAR ACOUSTIC SIGNALS, AND CORRESPONDING DEVICE
    Publication number: 20180063638
    Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.
    Type: Application
    Filed: March 30, 2017
    Publication date: March 1, 2018
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics Design and Application S.R.O., STMicroelectronics (Alps) SAS
    Inventors: Jean Claude Bini, Dragos Davidescu, Igor Cesko, Jonathan Cottinet
  • Method for transmitting and/or receiving audio signals
    Patent number: 9905262
    Abstract: A method for transmitting and/or receiving a potential aggressor audio signal includes a transmission and/or a reception of successive groups of data timed by a first clock signal within respective successive frames synchronized by a second clock signal. In the presence of a risk of interference of the potential aggressor audio signal with a different, potential victim, signal, during the transmission or reception of the potential aggressor audio signal, the frequency of the first clock signal is modified while keeping the frequency of the second clock signal unchanged.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: February 27, 2018
    Assignees: STMICROELECTRONICS (ALPS) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Jonathan Cottinet, Jean Claude Bini
  • Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
    Patent number: 9899476
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: February 20, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • Method for writing into and reading a multi-levels EEPROM and corresponding memory device
    Patent number: 9899090
    Abstract: During a phase of programming the cell, a first voltage is applied to the source region and a second voltage, higher than the first voltage, is applied to the drain region until the cell is put into conduction. The numerical value of the item of data to be written is controlled by the level of the control voltage applied to the control gate and the item of data is de facto written with the numerical value during the putting into conduction of the cell. The programming is then stopped.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: February 20, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: François Tailliet
  • Secure method for processing content stored within a component, and corresponding component
    Patent number: 9900151
    Abstract: A method for processing content stored on a component is disclosed. A first partition of a first memory is encrypted with a first encryption key and a second partition of the first memory is encrypted with a second encryption key. The second encryption key is different from the first encryption key. The first encryption key is stored in a storage register of the component and the second encryption key is stored in a first location of a non-volatile memory. A memory address of the first location is stored in the first partition of the first memory.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: February 20, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Fabrice Marinet, Mathieu Lisart
  • Integrated circuit power supply regulator
    Patent number: 9891639
    Abstract: The current signature of an electronic function is masked by controlling a current source that supplies power for the electronic function is controlled in a dynamically-varying manner. Excess current is detected and compared to a threshold. If the detected excess current meets the threshold, the operation of the electronic function is modified, for example by controlling a clock.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Fabrice Marinet
  • NFC device with multiple secure elements
    Patent number: 9894469
    Abstract: An NFC device includes first and second secure elements, an NFC router, and a processor. A method involves emulating, by the NFC router in response to a command from the processing device, an RF card emulation transaction. The RF card emulation transaction includes transmitting by the NFC router a command to the first and second secure elements to verify the presence of NFC transaction applications in the first and second secure elements. The method also includes receiving, by the NFC router, responses from the first and second secure elements and a new RF message from an NFC terminal. The responses indicate the NFC transaction applications stored by the first and second secure elements, and the new RF message relates to an NFC transaction. The new RF message is routed to the first or second secure element based on the responses.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: February 13, 2018
    Assignees: Proton World International N.V., STMicroelectronics (Rousset) SAS
    Inventors: Olivier Van Nieuwenhuyze, Jean Marc Grimaud, Arach Mohammed Brahim
  • CIRCUIT AND METHOD FOR PROTECTING A VOLTAGE REGULATING CIRCUIT AGAINST ELECTROSTATIC DISCHARGES
    Publication number: 20180041024
    Abstract: An integrated circuit includes a voltage regulating circuit in the form of only one transistor, or a group of several transistors in parallel, that are connected between first and second terminals configured to be coupled to an antenna. A control circuit operates to make the voltage regulating circuit inactive when a pulse generated by an electrostatic discharge event appears at one of the first and second terminals, regardless of the direction of flow of the pulse between the first and second terminals. An electrostatic discharge circuit is further provided to address the electrostatic discharge event.
    Type: Application
    Filed: February 17, 2017
    Publication date: February 8, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Nicolas Demange
  • Method for managing contactless communications and contactless charging within a system, and corresponding system
    Patent number: 9887741
    Abstract: A system includes an antenna, and communications circuitry coupled to the antenna and configured for at least one of receiving and transmitting information via the antenna based on a contactless communications protocol. A charger is configured for contactless charging a power supply module via the antenna. A controller is configured for selectively operating the communications circuitry and the charger.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: February 6, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pierre Rizzo, Anthony Tornambe
  • Method and device of memory space management
    Patent number: 9886380
    Abstract: A virtual memory is partitioned into virtual partitions, each partition being subdivided into virtual sub-partitions and each sub-partition corresponding to a combination of multiple sectors of identical or different sizes of a physical memory. When an allocation request is made for a virtual memory space having a given memory size, a free partition is selected, a virtual sub-partition is selected corresponding to a combination of sectors having a minimum total size covering the given memory size of the virtual memory to be allocated, and free sectors of the physical memory are selected corresponding to the selected combination. A determination is made of a correspondence table between the selected virtual partition and the initial physical addresses of the selected free sectors, and a virtual address is generated.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: February 6, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christophe Arnal, Roland Van Der Tuijn
  • PREVENTION OF PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS IN AN INTEGRATED CIRCUIT
    Publication number: 20180025990
    Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 25, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Jean-Philippe Escales
  • Metallic device having mobile element in a cavity of the BEOL of an integrated circuit
    Patent number: 9875870
    Abstract: In order, for example, to improve the ohmic contact between two metal pieces located at a metallization level, these two metal pieces are equipped with two offset vias located at the metallization level and at least partially at the via level immediately above. Each offset via comprises, for example, a nonoxidizable or substantially nonoxidizable compound, such as a barrier layer of Ti/TiN.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: January 23, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christian Rivero, Pascal Fornara, Sebastian Orellana
  • Method for managing a fail row of the memory plane of a non volatile memory and corresponding memory device
    Patent number: 9875798
    Abstract: A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: January 23, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Gineuve Alieri
  • EEPROM cell with charge loss
    Patent number: 9874856
    Abstract: An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: January 23, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Vertical memory cell with non-self-aligned floating drain-source implant
    Patent number: 9876122
    Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: January 23, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Marc Mantelli, Stephan Niel, Arnaud Regnier, Francesco La Rosa, Julien Delalleau