Patents Assigned to STMICROELECTRONICS (ROUSSET)
  • Detection of the authenticity of an electronic circuit or of a product containing such a circuit
    Patent number: 9870489
    Abstract: A method of authenticating a slave device. The method includes initializing, by a host device, a charge retention circuit of the slave device, and receiving, by the host device, an indication of a discharge time of the charge retention circuit. The host device authenticates the slave device based on the received indication of the discharge time of the charge retention device.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 16, 2018
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.
    Inventors: Jean-Louis Modave, Fabrice Marinet, Denis Farison
  • Method for estimating a time invariant transmission channel, and corresponding receiver
    Patent number: 9866274
    Abstract: A method is for processing an analog channel signal from a transmission channel. The method may include converting of the analog channel signal to a digital channel signal, and performing a channel estimation digital processing of the digital channel signal. The channel estimation digital processing may include for at least one frame, generating transfer functions of the transmission channel, the transfer functions respectively associated with reference symbols of the frame, and averaging processing of the transfer functions to generate an average transfer function. The method may include decoding of symbols of the frame following the reference symbols using the average transfer function.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: January 9, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pierre Demaj, Yoann Bouvet
  • Method for controlling the tuning to a communications frequency of an antenna connected to a component designed for contactless communication and corresponding system
    Patent number: 9853677
    Abstract: A system includes an antenna, and a contactless component for receiving and/or transmitting information via the antenna according to a contactless communications protocol. An inductive-capacitive network is connected between the antenna and the contactless component and includes a configurable filter for filtering electromagnetic interference. A processor modifies an impedance of the configurable filter for filtering electromagnetic interference to control frequency tuning of the antenna.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: December 26, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Alexandre Tramoni
  • Method for managing the dialogue between an item of equipment and at least one multi-application object
    Patent number: 9851703
    Abstract: A portable object includes an antenna and a processor coupled to the antenna. The processor is configured to communicate with an item of equipment according to a contactless communication protocol that contains an anticollision procedure. The processor is also configured to execute a plurality of software modules. The software modules include application modules and a triggering module, which is configured to cause a triggering of the anticollision procedure between the single portable object and the item of equipment. The processor is configured to cause a signal, which is generated by executing the triggering module, to be transmitted from the antenna to the time of equipment.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: December 26, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christophe Cataldo, Sophie Gabriele, Christophe Mani, Fabrice Romain
  • Method for generation of electrical power within a three-dimensional integrated structure and corresponding link device
    Patent number: 9847373
    Abstract: Method for generation of electrical power within a three-dimensional integrated structure comprising several elements electrically interconnected by a link device, the method comprising the production of a temperature gradient in at least one region of the link device resulting from the operation of at least one of the said elements, and the production of electrical power using at least one thermo-electric generator comprising at least one assembly of thermocouples electrically connected in series and thermally connected in parallel and contained within the said region subjected to the said temperature gradient.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: December 19, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • DEVICE FOR DETERMINING THE MOVEMENT OF A ROTARY ELEMENT, PARTICULARLY FOR READINGS OF WATER AND/OR GAS METERS
    Publication number: 20170350730
    Abstract: A rotary element is equipped with a pattern representing a reflected binary code on at least three bits. A detection circuit is configured to sense the pattern and deliver an incident signal encoded in reflected binary code on at least three bits. The incident signal is converted by a transcoding circuit into an intermediate signal encoded in reflected binary code on two bits. A decoding stage decodes the intermediate signal and outputs at least one clock signal representing the amount of rotation of the rotary element and a direction signal representing the direction of rotation. A processing circuit determines the movement of the rotary element, and has at least one general purpose timer designed to receive the at least one clock signal and direction signal.
    Type: Application
    Filed: December 14, 2016
    Publication date: December 7, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Vincent Onde
  • Regulator with low dropout voltage and improved stability
    Patent number: 9836070
    Abstract: The regulator with a low dropout voltage comprises an error amplifier comprising a differential pair of input transistors and a circuit with folded cascode structure connected to the output of the said differential pair, an output stage connected to the output node of the error amplifier, and a Miller compensation capacitor connected between the output stage and the cascode node on the output side (XP) of the cascode circuit; the error amplifier furthermore comprises at least one inverting amplifier module in a feedback loop between the said cascode node and the gate of the cascode transistor of the cascode circuit connected between the said cascode node and the said output node.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: December 5, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Thierry Soude
  • Method for estimating a cyclostationary transmission channel, and corresponding receiver
    Patent number: 9838077
    Abstract: A method is for processing an analog channel signal from a transmission channel. The analog channel signal conveys frames, the transmission channel being linear and cyclostationary for a duration of a frame. The method may include converting of the analog channel signal into a digital channel signal, and performing channel estimations for the frame based upon the digital channel signal to generate a sequence of N transfer functions of the transmission channel. Each of the sequence of N transfer functions may be respectively associated with N successive time slices. The method may include decoding at least some symbols of the frame using, for each of the symbols, a transfer function associated with a successive time slice including a respective symbol.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: December 5, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pierre Demaj, Yoann Bouvet
  • Electronic chip
    Patent number: 9837364
    Abstract: An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity type arranged alternately and contiguously on a region of the first conductivity type; two detection contacts arranged at the ends of each second bar; a circuit for detecting the resistance between the detection contacts of each second bar; insulating trenches extending in the second bars down to a first depth between circuit elements; and insulating walls extending across the entire width of each second bar down to a second depth greater than the first depth.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: December 5, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Mathieu Lisart, Jimmy Fort
  • Receiver for processing a signal coming from a transmission channel
    Patent number: 9838080
    Abstract: A method is for processing a channel analog signal coming from a transmission channel. The method may include converting the channel analog signal into a channel digital signal, and detecting a state of the transmission channel based on the channel digital signal to detect whether the transmission channel is, over an interval of time, one or more of linear and time invariant and linear and cyclostationary.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: December 5, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yoann Bouvet, Pierre Demaj
  • Read performance of a non-volatile memory device, in particular a non-volatile memory device with buried selection transistor
    Patent number: 9825186
    Abstract: The non-volatile memory device comprises memory cells each comprising a selectable state transistor having a floating gate and a control gate. The state transistor is of the depletion-mode type and is advantageously configured so as to have a threshold voltage that is preferably negative when the memory cell is in a virgin state. When the memory cell is read, a read voltage of zero may then be applied to the control gate and also to the control gates of the state transistors of all the memory cells of the memory device.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: November 21, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • PULSE COUNTING CIRCUIT
    Publication number: 20170324403
    Abstract: A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.
    Type: Application
    Filed: November 22, 2016
    Publication date: November 9, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Jean Nicolai, Albert Martinez
  • MULTIPLEXER STRUCTURE
    Publication number: 20170324405
    Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.
    Type: Application
    Filed: November 28, 2016
    Publication date: November 9, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Albert Martinez, Michel Agoyan
  • GENERATOR OF NUMBERS OF OSCILLATIONS
    Publication number: 20170324409
    Abstract: A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.
    Type: Application
    Filed: November 28, 2016
    Publication date: November 9, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Albert Martinez, Michel Agoyan, Jean Nicolai
  • Prevention of premature breakdown of interline porous dielectrics in an integrated circuit
    Patent number: 9812399
    Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: November 7, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Jean-Philippe Escales
  • Combined flow and low-power state control using same lines between interfaces
    Patent number: 9813221
    Abstract: A method for controlling a low-power state of a pair of serial interfaces using a pair of flow-control signal lines may include enabling a first of the flow-control lines by a first one of the interfaces for signaling a transmission request to the second interface. The method may also include, in response to the transmission request, waking up to a live state from a low-power state and enabling a second flow-control line for signaling a transmission authorization to the first interface. In response to the transmission authorization, the method may include initiating a transmission of a message to the second interface, and upon reaching an offset before the end of the message transmission, disabling the first flow-control line by the first interface. The method may also include, at the end of the message transmission, disabling the second flow-control line and going back into the low-power state.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: November 7, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christophe Arnal, Roland Van Der Tuijn
  • MOS TRANSISTOR STRUCTURE, IN PARTICULAR FOR HIGH VOLTAGES USING A TECHNOLOGY OF THE SILICON-ON-INSULATOR TYPE
    Publication number: 20170317106
    Abstract: An integrated circuit is formed using a substrate of a silicon-on-insulator type that includes a carrier substrate and a stack of a buried insulating layer and a semiconductor film on the carrier substrate. A first region without the stack separates a second region that includes the stack from a third region that also includes the stack. An MOS transistor has a gate dielectric region formed by a portion of the buried insulating layer in the second region and a gate region formed by a portion of the semiconductor film in the second region. The carrier substrate incorporates doped regions under the first region which form at least a part of a source region and drain region of the MOS transistor.
    Type: Application
    Filed: November 28, 2016
    Publication date: November 2, 2017
    Applicants: STMicroelectronics (Rousset 2) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Boivin, Franck Arnaud, Gregory Bidal, Dominique Golanski, Emmanuel Richard
  • Method and device for generating an adjustable bandgap reference voltage
    Patent number: 9804631
    Abstract: A circuit includes a first PMOS transistor that includes a first PMOS source coupled to a first input node, a first PMOS gate, and a first PMOS drain. A second PMOS transistor includes a second PMOS source coupled to a second input node, a second PMOS gate, and a second PMOS drain coupled to the second PMOS gate. A first resistor coupled between the first PMOS source and a ground node. A first diode element coupled between the first resistor and the ground node and a second diode element coupled between the second PMOS source and the ground node. A third PMOS transistor includes a third PMOS gate, a third PMOS source coupled to a supply node, and a third PMOS drain coupled to the first input node. A fourth PMOS transistor includes a fourth PMOS gate coupled to the third PMOS gate, a fourth PMOS source coupled to the supply node, and a fourth PMOS drain coupled to the second input node.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: October 31, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Thierry Soude
  • Protection of a security element coupled to an NFC circuit
    Patent number: 9801070
    Abstract: A method and a device for protecting a security module connected to a near-field communication router in a telecommunication device, wherein a transmission between the router and the security module is only allowed in the presence of a radio frequency communication flow detected by the router.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: October 24, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Alexandre Charles
  • STACK OF LAYERS FOR PROTECTING AGAINST A PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS WITHIN AN INTEGRATED CIRCUIT
    Publication number: 20170301623
    Abstract: A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region.
    Type: Application
    Filed: December 14, 2016
    Publication date: October 19, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Jean-Philippe Escales