Abstract: Memory devices such as phase change memory (PCM) devices utilizing Ovonic Threshold Switching (OTS) selectors may be used to fill the gap between dynamic random-access memory (DRAM) and mass storage and may be incorporated in high-end microcontrollers. Since the programming efficiency and reading phase efficiency of such devices is directly linked to the leakage current of the OTS selector as well as sneak-path management, a sense amplifier disclosed herein generates an auto-reference that takes into account the leakage currents of unselected cells and includes a regulation loop to compensate for voltage drop due to read current sensing. This auto-referenced sense amplifier, built utilizing the principle of charge-sharing, may be designed on a 28 nm fully depleted silicon-on-insulator (FDSOI) technology, provides robust performance for a wide range of sneak-path currents and consequently for a large range of memory array sizes, and is therefore suitable for use in embedded memory in high-end microcontroller.

Abstract: A method of manufacturing a contact on a semiconductor region includes a step of forming a stack of layers on lateral walls and at a bottom of an orifice (aligned with the semiconductor region) crossing a dielectric region along a longitudinal direction. The step of forming step is carried out from a first surface of the dielectric region and includes forming a polysilicon layer and a layer of a first metal in contact with the polysilicon layer. The first metal is preferably a metal selected from the group of transition metals and is well suited to forming with the polysilicon layer a metal silicide. The method further includes a step of performing thermal anneal causing a reaction between the first metal and the polysilicon layer to produce a layer of metal silicide. At least a portion of that layer of metal silicide extends in the longitudinal direction of the orifice.

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

Abstract: A contactless communication device includes an electronic integrated circuit chip and an antenna coupled to the electronic integrated circuit chip to supply an electric signal for powering the electronic integrated circuit chip. An ambient luminosity detection element is coupled to the electronic integrated circuit chip. An ambient luminosity level measured by the ambient luminosity detection element is supplied to the electronic integrated circuit chip for comparison to a darkness threshold. A contactless communication is authorized only when the measured ambient luminosity level is greater than the darkness threshold.

Abstract: A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

Abstract: An embodiment transistor comprises a semiconductor drain region delimited by a first trench, and, in the first trench, a first electrically conductive element electrically coupled to a node of application of a potential closer to a drain potential of the transistor than to a source potential of the transistor.

Abstract: A method includes detecting, by a first near-field communication device, the presence of a second near-field communication device. In a case where the second device is intended to be charged in near-field by the first device, the method further includes adjusting, by a control device, an impedance of an impedance matching circuit forming part of a near-field communication circuit of the first device.

Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

Abstract: An embodiment method for determining a carry digit indicator bit of a first binary datum includes a step for processing of the first binary datum masked by a masking operation, and not including any processing step of the first binary datum.

Abstract: A method of configuring a contactless communication device is provided. The contactless communication device includes integrated circuits hosting at least two applications compatible with the same communication protocols or compatible with the same communication protocol and using different communication parameters and a contactless communication circuit. The method includes detecting, by the contactless communication circuit, an interruption of a transaction initiated by a proximity coupling reader.

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.

Abstract: Unclonable function circuitry includes a plurality of pairs of phase-change memory cells in a virgin state, and sensing circuitry coupled to the plurality of pairs of phase-change memory cells in the virgin state. The sensing circuitry identifies a subset of the plurality of pairs of phase-change memory cells in the virgin state based on a reliability mask. Signs of differences of effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state are sensed by the sensing circuitry. The sensing circuitry generates a string of bits based on the sensed signs of differences in the effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state. Processing circuitry coupled to the unclonable function circuitry, in operation, executes one or more operations using the generated string of bits.

Abstract: A device includes an application processor and a hardware signal processor coupled to the application processor. The hardware signal processor, in operation: receives a command pre-list during an initialization phase of the hardware signal processor, the command pre-list including a plurality of function describers, each of the plurality of function describers being associated with a respective plurality of parameter describers; generates a command list based on the command pre-list during the initialization phase; and stores the command list in memory circuitry.

Abstract: An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.

Abstract: A near-field communication device operates to transmit data by near-field communications techniques to another device. The near-field communication device includes a memory that stores a message to be transmitted in an ASCII format. The message is retrieved from the memory and transmitted using the near-field communications techniques in an ASCII format.

Abstract: In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.