Patents Assigned to STMICROELECTRONICS (ROUSSET)
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Publication number: 20230223448Abstract: A method of manufacturing a radio frequency switch includes the steps of: forming a first silicide layer on a second conductive or semiconductor layer; forming a third insulating layer on the first layer; forming a cavity in the third insulating layer reaching the first silicide layer; forming a fourth metal layer in the cavity in contact with the first silicide layer; performing a non-oxidizing annealing; and filling the cavity with a conductive material. The first silicide layer is provided on one or more of the gate, source, and drain of a transistor forming the radio frequency switch.Type: ApplicationFiled: January 6, 2023Publication date: July 13, 2023Applicant: STMicroelectronics (Rousset) SASInventors: Pascal FORNARA, Christian RIVERO, Franck JULIEN
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Publication number: 20230223358Abstract: Integrated circuits are supported by a semiconductor substrate wafer. Each integrated circuit includes an electrically active area. A thermally conductive protective structure is formed around the active areas of the various integrated circuits along scribe paths. The protective structure is located between the electrically active areas of the integrated circuits and a laser ablation area of the scribe paths. Separation of the integrated circuits is performed by scribing the semiconductor substrate wafer along the scribe paths. The process for scribing includes performing a laser ablation in the laser ablation area and then performing one of an etching or a physical scribing.Type: ApplicationFiled: January 6, 2023Publication date: July 13, 2023Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SASInventors: Carlos Augusto SUAREZ SEGOVIA, David PARKER, Chantal TROUILLER, Alexandre MALHERBE, Stephan NIEL
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Publication number: 20230223989Abstract: A near-field communication circuit of a first NFC device alternates, in low power mode, between: first phases of emission of field bursts and second phases spanning an entire duration separating two successive first phases. Each second phase includes a field detector enabling phase. In one implementation, the field detector enabling phase extends all along a duration of the second phase. In an alternate implementation, the field detector enabling phase is interrupted by field detector disabling phases. Each field detector disabling phase has a duration shorter than a minimum duration of each first phase.Type: ApplicationFiled: January 6, 2023Publication date: July 13, 2023Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics SA, STMicroelectronics Razvoj Polprevodnikov D.O.O.Inventors: Alexandre TRAMONI, Kosta KOVACIC, Florent SIBILLE, Nicolas CORDIER, Anthony TORNAMBE, Jean Remi RUIZ, Guillaume JAUNET
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Patent number: 11698651Abstract: The present invention concerns an electronic circuit power supply device, configured to: flow, through a first conductor connected to a node, a first current that is an image of a second current consumed by the electronic circuit; flow a third current through a second conductor connected to the node, a first branch of a current mirror conducting the third current; flow a fourth constant current through a third conductor connected to the node; consume a fifth current that is an image of the third current; and regulate a potential of the node by acting on a gate potential of a transistor electrically in series with a second branch of the current mirror.Type: GrantFiled: August 11, 2021Date of Patent: July 11, 2023Assignee: STMicroelectronics (Rousset) SASInventors: Nicolas Demange, Nicolas Borrel, Jimmy Fort
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Patent number: 11699224Abstract: A device includes image generation circuitry and convolutional-neural-network circuitry. The image generation circuitry, in operation, generates a digital image representation of a wafer defect map (WDM). The convolutional-neural-network circuitry, in operation, generates a defect classification associated with the WDM based on: the digital image representation of the WDM and a data-driven model associating WDM images with classes of a defined set of classes of wafer defects and generated using a training data set augmented based on defect pattern orientation types associated with training images.Type: GrantFiled: November 9, 2021Date of Patent: July 11, 2023Assignee: STMICROELECTRONICS (ROUSSET) SASInventor: Laurent Bidault
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Patent number: 11700520Abstract: Devices and methods for configuration of a mobile terminal including a near-field communication device and a radio communication device separate from the near-field communication device are provided. One such method includes determining, by the radio communication device, an identifier of a wireless local network within a range of the mobile terminal. The method further includes selecting, from a configuration table, at least one configuration parameter of a plurality of sets of configuration parameters of the near-field communication device according to the identifier, and applying the at least one configuration parameter to the near-field communication device.Type: GrantFiled: December 15, 2020Date of Patent: July 11, 2023Assignees: STMicroelectronics (Rousset) SAS, Proton World International N.V.Inventors: Olivier Van Nieuwenhuyze, Alexandre Tramoni, Pierre Rizzo
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Patent number: 11696438Abstract: An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.Type: GrantFiled: July 14, 2020Date of Patent: July 4, 2023Assignee: STMicroelectronics (Rousset) SASInventor: François Tailliet
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Publication number: 20230207449Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.Type: ApplicationFiled: March 2, 2023Publication date: June 29, 2023Applicant: STMicroelectronics (Rousset) SASInventor: Abderrezak MARZAKI
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Publication number: 20230198514Abstract: The present disclosure relates to a device comprising a first transistor and a first circuit comprising first and second terminals, the first circuit being configured to generate a first voltage representing the temperature of the first transistor, a first terminal of the first circuit being coupled to the drain of the first transistor.Type: ApplicationFiled: December 12, 2022Publication date: June 22, 2023Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (ROUSSET) SASInventors: Antoine PAVLIN, Vanni POLETTO, Vincenzo RANDAZZO
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Patent number: 11680835Abstract: An oscillating analog signal includes a succession of dampened oscillations. That oscillating analog signal is conditioned to generate an output signal including only oscillations of the oscillating analog signal which have an amplitude smaller than a first threshold. The output signal is then processed by a processing unit, where the first threshold is compatible with a maximum level of voltage tolerable by the processing unit.Type: GrantFiled: January 22, 2021Date of Patent: June 20, 2023Assignee: STMicroelectronics (Rousset) SASInventors: Nicolas Froidevaux, Laurent Lopez
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Publication number: 20230189149Abstract: In the case of a potential detection, by a first near field communication (NFC) device, of a second NFC device, a validation of this detection is performed according to the time variation gradient of at least one environmental condition of the first device. A value of one of an amplitude and an phase of a signal across an oscillating circuit of the first NFC device is compared to first thresholds to potentially detect the second NFC device. Validation of detection occurs when one of the amplitude and the phase of the signal is outside the first thresholds adjusted as a function of the time variation gradient. Validation detection also occurs when one of the amplitude and the phase of the signal adjusted as a function of the time variation gradient is outside the first thresholds.Type: ApplicationFiled: December 8, 2022Publication date: June 15, 2023Applicant: STMicroelectronics (Rousset) SASInventors: Nicolas CORDIER, Guillaume JAUNET
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Publication number: 20230187922Abstract: Embodiments are directed to electronic fuse devices and systems. One such electronic fuse includes current sensing circuitry that senses a current in a conductor coupled between a power supply and a load, and generates a current sensing signal indicative of the sensed current. I2t circuitry receives the current sensing signal and determines whether the sensed current exceeds an I2t curve of the conductor. The electronic fuse further includes at least one of external MOSFET temperature sensing circuitry that senses a temperature of an external MOSFET coupled to the conductor, low current bypass circuitry that supplies a reduced current to the load in a low power consumption mode during which the external MOSFET is in a non-conductive state, or desaturation sensing circuitry that senses a drain-source voltage of the external MOSFET.Type: ApplicationFiled: December 12, 2022Publication date: June 15, 2023Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (ROUSSET) SASInventors: Vincenzo RANDAZZO, Alberto MARZO, Giovanni SUSINNA, Vanni POLETTO, Antoine PAVLIN, CalogeroAndrea TRECARICHI, Mirko DONDINI, Roberto CRISAFULLI, Enrico CASTRO, Romeo LETOR
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Patent number: 11671146Abstract: An embodiment of the present description concerns a method wherein a duration of a periodic step of activation of a near-field communication circuit of a first device is calibrated according to a time interval between an activation of the circuit and a reception, by the first device, of a message transmitted by a second device.Type: GrantFiled: October 12, 2021Date of Patent: June 6, 2023Assignee: STMicroelectronics (Rousset) SASInventor: Alexandre Tramoni
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Patent number: 11670385Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.Type: GrantFiled: December 21, 2021Date of Patent: June 6, 2023Assignee: STMicroelectronics (Rousset) SASInventors: François Tailliet, Chama Ameziane El Hassani
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Patent number: 11670956Abstract: An integrated circuit includes: a primary supply stage including a primary supply node, the primary supply stage being configured to deliver a primary supply voltage to the primary supply node; a secondary supply stage including a secondary supply node, the secondary supply stage being configured to deliver a secondary supply voltage to the secondary supply node; a supply-switching circuit; a pre-charging circuit controllably coupled to the secondary supply node via the supply-switching circuit; and a volatile memory circuit controllably coupled to the primary supply node and the secondary supply node via the supply-switching circuit, wherein the switching circuit is configured to connect a supply of the volatile memory circuit either to the primary supply node in a primary supply mode, or to the secondary supply node in a secondary supply mode.Type: GrantFiled: August 27, 2021Date of Patent: June 6, 2023Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Laurent Truphemus, Sebastien Ortet
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Patent number: 11671078Abstract: A device for generating first clock signals includes first circuits, each including a ring oscillator delivering one of the first clock signals and being connected to a first node configured to receive a first current. A circuit selects one the first clock signals, and a phase-locked loop delivers a second signal which is a function of a difference between a frequency of the first selected clock signal and a set point frequency. Each first circuit supplies the first node with a compensation current determined by the second signal, when this first circuit delivers the selected clock signal and operates in controlled mode.Type: GrantFiled: November 5, 2021Date of Patent: June 6, 2023Assignee: STMicroelectronics (Rousset) SASInventor: Bruno Gailhard
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Publication number: 20230170938Abstract: The present disclosure relates to a method for aligning a smartphone providing NFC wireless power for charging a battery of a device, the method comprising: emitting, with a first NFC antenna of the smartphone, an NFC field for wirelessly charging the battery of the device comprising a second NFC antenna; obtaining, with the smartphone, a measured value of a signal representative of the NFC field strength between the smartphone and the device; determining, by the smartphone, a range of values of a plurality of ranges of values the measured value belongs; and emitting, by the smartphone, at least one notification signal to a user with a frequency determined by the determined range of values.Type: ApplicationFiled: January 12, 2023Publication date: June 1, 2023Applicants: STMICROELECTRONICS LTD, STMICROELECTRONICS (ROUSSET) SASInventors: Chia Hao CHEN, Nicolas CORDIER
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Publication number: 20230168821Abstract: A system-on-chip includes a processor, a memory and a memory interface coupled to the processor and to the memory. The processor, in operation, generates memory access requests. The memory includes one or more physical banks divided into a succession of sectors, each sector having a size equal to a smallest erasable size of the memory. The memory interface, in operation, responds to receiving memory configuration information by storing logical memory bank configuration information in the one or more configuration registers, the logical memory bank configuration information assigning each sector of the one or more physical banks of the memory to a respective logical memory bank of one or more logical memory banks. The memory interface, in operation, controls access to the memory by the processor based on the logical memory bank configuration information stored in the one or more configuration registers.Type: ApplicationFiled: November 21, 2022Publication date: June 1, 2023Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (ROUSSET) SASInventors: Francesco BOMBACI, Andrea TOSONI
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Patent number: 11663435Abstract: In an embodiment a method for dynamic power control of a power level transmitted by an antenna of a contactless reader is disclosed. The method may include supplying a power to the antenna and performing at least one power adjusting cycle for adjusting a power level during a contactless transaction with a transponder, each power adjusting cycle including modifying the power supplied to the antenna to a predetermined level of power, performing a first measuring of a loading effect on the antenna at the predetermined level of power and adjusting the power level according to the measured loading effect.Type: GrantFiled: November 12, 2020Date of Patent: May 30, 2023Assignees: STMicroelectronics (Rousset) SAS, STMicroeleclroncs Razvoj Polprevodnikov D.O.O.Inventors: Kosta Kovacic, Alexandre Tramoni
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Patent number: 11663314Abstract: An embodiment device comprises a first processing unit configured to process an initial data line and deliver a first processed data line, a first delay unit coupled to the output of the first processing unit and configured to deliver a delayed first processed data line delayed by a first delay, a second delay unit configured to deliver the delayed initial data line delayed by a second delay, a second processing unit coupled to the output of the second delay unit and configured to process the delayed initial data line and deliver a delayed second processed data line, and a comparison unit configured to compare the contents of the delayed first and second processed data lines and deliver a non-authentication signal if the contents are not identical, the first and second delays being equal to a variable value.Type: GrantFiled: October 15, 2020Date of Patent: May 30, 2023Assignee: STMicroelectronics (Rousset) SASInventor: Olivier Giaume
