Abstract: A voltage booster circuit including an input for receiving a supply voltage, a plurality of stages for producing an output voltage from the supply voltage by the transfer of charges between at least two of the plurality of stages, and circuit for coupling and decoupling stages to vary the number of stages operatively connected together. A method for producing an output voltage from a supply voltage by using a voltage booster circuit, the circuit includes an input for receiving the supply voltage, a plurality of stages, and a selection switch for the selective isolation of the stages or for the selective connection of the stage. The method includes the following steps: starting the circuit; comparing the value of the output voltage with a decrementation threshold; and decreasing the number of stages which are connected if the decrementation threshold is reached by the value of the output voltage.

Abstract: A non-volatile electrically erasable and programmable memory provides both a SDP (software data protection) function and an OTP (one-time protection) function. The memory comprises a memory array having a plurality of memory cells each for storing an information bit. The memory further comprises at least one supplementary cell for storing a first state bit pertaining to the write-accessible (or non-write accessible) state of all the memory cells of the memory array, and at least one other supplementary cell for storing a second state bit relating to the blank state (or non-blank state) of a group of memory cells designed to be programmed only once by the user. A common management circuit for the SDP and OTP cells is located outside the memory array.

Abstract: The present invention relates to an assembly of two pairs of diodes in a single semiconductor substrate of a first type of conductivity, the first pair including a first diode in series with a second diode, the second pair including a third diode in series with a fourth diode, the two pairs of diodes being arranged in parallel. Each of the first and third diodes includes neighboring regions of distinct types of conductivity formed in a lightly-doped well of the second type of conductivity, these wells being separated; each of the second and fourth diodes includes separated regions of distinct types of conductivity; and metallizations connect the electrodes of the diodes to form the desired series-to-parallel assembly.

Abstract: A method for the generation of voltage for the programming or erasure of a non-volatile memory cell is disclosed. Also disclosed is a circuit and a computer readable medium which implement the method. During an operation of programming or erasure in the memory, the slope P of the write voltage ramp is adapted to the number of memory cells to be programmed or erased simultaneously during this operation. This method is particularly useful in the field of non-volatile, electrically erasable and programmable memories.

Abstract: In a device for programming EPROM-Flash type memory cells of memory words of a memory, a bit line of a memory cell of a given rank of the first word and at least one bit line of a memory cell of the same rank in a word that is horizontally adjacent to this first word are connected together to two common programming connections by means of a bias circuit, and the bias circuit comprises two bias voltage inputs and one bias voltage output. The programming method consists in the successive programming, during different programming cycles, of the different cells of this first word and, during the same programming cycle, a different cell, of the same rank, in at least one word that is different from this first word is programmed.

Abstract: A circuit for the generation of a high ramp voltage for the supply of voltage to a capacitive load, in particular a high voltage for the programming or erasure of at least one memory cell of a non-volatile memory, comprises floating-gate transistors as storage elements. This generation circuit comprises a P type load transistor connected by its source to the output of a voltage booster delivering a high direct and constant voltage (HIV), by its drain to the load, the high ramp voltage being available at this drain, and by its control gate to a control feedback circuit to control the load current. This circuit achieves automatic control over the slope of the high ramp voltage (Vpp). Application to the generation of a high ramp voltage whose slope is smaller than a critical slope and the maximum value is high.

Abstract: A method for locating possible defects on an opaque layer deposited on a production wafer of a semiconductor circuit, consisting in locally radiating an upper surface of the wafer by means of a laser, and detecting the occurrence of a current in a diode constituted by a PN junction placed under the opaque layer to be examined.

Abstract: A voltage circuit generates a programming or erasure voltage for programming or erasing a floating-gate memory. The voltage generator circuit includes a charge pump to provide a pumped voltage and a shaping circuit to provide the programming or erasing voltage from the pumped voltage. A switching circuit enables the pumped voltage to reach a sufficient level before the shaping circuit generates the programming or erasure voltage.

Abstract: A sequential access memory comprises N register elements each storing an information bit. These N register elements are divided into P groups each comprising L elements. In a first phase of operation whose duration corresponds to P-1 consecutive periods of the clock signal, only the last elements of each group are activated and are furthermore series-connected. In a second phase of operation whose duration corresponds to a single period of the clock signal, all the elements are activated simultaneously, the groups of elements being furthermore series-connected. The advantage is that it enables a reduction in the dynamic consumption of the memory.

Abstract: An integrated circuit comprises at least one differential input stage. The differential input stage includes an input circuit and a shaping circuit. The input circuit comprises a first portion and a second portion for providing two pairs of differential signals. The propagation times of the first and second circuit portions are preferably substantially identical. The shaping circuit differentiates each of the two pairs of differential signals and combines them to obtain a single binary type of signal.

Abstract: In a pulse filtering device, the pulse signal is sampled to enable the counting of this signal by an asynchronous counter. A pulse of calibrated duration is generated when the counting reaches a predetermined number.

Abstract: An LED driver drives a plurality of light emitting diodes (LEDs) having first terminals connected to a common output stage and second terminals respectively receiving different, suitably rectified, phases of a sinusoidal signal. An output stage of the LED driver includes a first bipolar transistor coupled between a first supply terminal and the first terminals of the LED's. A first MOS transistor drives the base of the first bipolar transistor. The gate of the first MOS transistor is coupled to a first reference voltage. A second bipolar cascode transistor is connected in series with the first MOS transistor and biased by a second reference voltage such that the voltage across the first MOS transistor does not exceed a limit value.

Abstract: The present invention relates to a memory cell including two sets each including first and second transistors connected between high and low potentials, the first transistor being a P-channel transistor and the second one an N-channel transistor. Both sets include a third and a fourth N-channel transistor. The third transistor is connected between the high potential and the control electrode of the second transistor. The fourth transistor is connected between the low potential and the control electrode of the second transistor. The drains of the first and second transistors of each set form storage nodes. The sources and drains of the third and fourth transistors form input/output nodes, distinct from the storage nodes.

Abstract: An analog switch formed from a MOS transistor switch includes means for applying to the bulk terminal of the transistor switch the voltage of either one of the two main terminals of the transistor switch as a function of the relation between the voltages of said main terminals.

Abstract: A circuit for restoring bits transmitted by an asynchronous signal includes a first comparator for comparing the level of the asynchronous signal with a first threshold adjusted as a function of the output of the first comparator during synchronization bursts of the asynchronous signal, and at least a second comparator for comparing the level of the asynchronous signal with a second threshold correlated to the first threshold.

Abstract: The invention relates to a dimensional control device for semiconductor wafer transport cassettes. Each cassette has a base from which extend vertical walls including horizontal grooves designed to receive wafers by lateral insertion. The device includes a seat provided with positioning guides of a cassette base; switches placed on the seat so that the actuation of all the switches by the positioned base indicate a suitable planarity of the base; a drawer mounted slidably on the seat so as to be engageable in the cassette in the insertion direction of the wafers, and having at least one template corresponding to a high position groove of the cassette; and a stop placed on the seat, at the side opposite to the drawer with respect to the cassette, to cause a tilting of the cassette when the drawer is moved towards the cassette and the template does not correspond to the cassette.

Abstract: A power supply voltage monitoring device includes a constant voltage generator, a comparator to compare the power supply voltage with a reference voltage output by the constant voltage generator and to control the state of an output terminal. The device also comprises a delay circuit to put the output terminal into a predetermined state (low) for a predetermined duration exceeding the duration of the transient conditions, while the voltage generator is being put into operation. The power supply voltage monitoring device may typically be applied in microprocessor equipment.

Abstract: The present invention relates to a power amplifier having an output stage in MOS technology, including an upper half-output stage comprised of two P-channel MOS power transistors mounted as a current mirror, a lower half-output stage comprised of two N-channel MOS power transistors mounted as a current mirror, an output terminal of the amplifier corresponding to the common drains of a first MOS transistor of the upper stage and of a first MOS transistor of the lower stage, and a control stage in bipolar technology for setting, according to a control voltage, two control currents of the half-output stages.

Abstract: The present invention concerns a method for the numerical scrambling by permutation of data bits in a programmable circuit comprising a control unit and at least one data bus (DBUS) to transmit data between the control unit and several memory circuits. It consists of having data on the bus either in a scrambled form or in an unscrambled form according to whether it is instructions data or not. And data in some of the memories is scrambled. The present invention also concerns a method for realising a permutation circuit.