Abstract: The invention relates to a method of manufacturing, on a silicon wafer, a plurality of integrated circuits and at least one test circuit, comprising steps of insulation of the silicon wafer by means of a reticle disposed in an exposure chamber provided with a diaphragm which allows to hide the non useful parts of the reticle. According to the invention, the method comprises an insulation (exposure) step performed by means of a reticle (130) comprising an insulation mask region (132) for integrated circuits together with at least one insulation mask region (133, 134, 135) for a test circuit. The insulation step includes one or more insulation steps during which the insulation mask region for test circuit is hidden by the diaphragm, and at least one insulation step during which the insulation mask region for test circuit is uncovered by the diaphragm, while all or part of the insulation mask for integrated circuit is hidden by the diaphragm.

Abstract: In a differential amplifier with asymmetrical outputs, the gates of the two load transistors are at the same specified potential and the voltage at the connection node between the load transistor and the amplifier transistor of one arm is stabilized by means of a compensation structure. This amplifier works at low VCC (e.g., less than 2 volts) while at the same time having high gain.

Abstract: An option configuration device in an integrated circuit including, for each option bit to be configured, a configuration stage that includes a first set of non-volatile memory cells parallel-connected between a first node and a ground connection, and a second set of non-volatile memory cells parallel-connected between a second node and a ground connection. The first and second nodes are each connected to an input of a read circuit including a differential amplifier.

Abstract: A device for demodulating a binary signal having a predetermined carrier frequency and phase-modulated by encoded pulses. The device includes a phase-locked loop circuit having a phase comparator followed by a low-pass filter and a voltage-controlled oscillator, which is voltage-controlled by the output of the filter. The voltage-controlled oscillator outputs a binary signal that is synchronous with the modulated signal and at a frequency N times the carrier frequency. The phase-locked loop circuit also includes a divider that divides by N the output signal of the oscillator and supplies the divided signal to one input of the phase comparator. Thus, a binary signal synchronous with the modulated signal and having a frequency equal to the carrier frequency is supplied to one input of the phase comparator. The other input of the phase comparator receives the modulated signal.

Abstract: This invention relates to a method for programming a Flash-EPROM type memory (1) comprising words of memory cells arranged in rows (23) and columns (31), in which a floating-gate transistor (7) acts as a storage device, the floating-gate transistors of the memory cells (2-9) in the same word (10) have their control gate connected to the same word line connection (30) and their source connected to the same main electrode (29) of a selection transistor (26), the other main electrode (28) of which is connected to a vertical word source connection (25), in which M memory cells (2, 2b) are programmed simultaneously in N different words (10, 200) during a single programming cycle, where M is less than the number P of memory cells in a word, and where M, N and P are integer numbers.

Abstract: A method is to characterize a process of ion implantation and includes a step of the measurement, by a spectroscopic ellipsometer, of the ellipsometric parameters (tan.psi., cos.delta.)of a film of organic resin present on the surface of a wafer that has received ion bombardment. The film of resin includes at least one upper layer of carbonized or damaged resin.

Abstract: A circuit for providing a D.C. voltage of high value from the output of a rectifying bridge on a capacitor of high capacitance, and for providing low supply voltages, including a first diode connected between the output of the rectifying bridge and the capacitor, first and second cascode-mounted transistors, circuitry for setting the potential of the control terminal of the first transistor, circuitry for reducing the potential of this control terminal when the rectified voltage exceeds a predetermined value, a regulation circuit connected at the connection node of the first and second transistors, and circuitry for applying, to the second transistor, a turn-on pulse of determined duration after the output voltage of the bridge has exceeded the determined value.

Abstract: An Exclusive-OR logic gate with four two-by-two complementary inputs and two complementary outputs. The structure of this Exclusive-Or gate is said to be symmetrical in that the gate has a propagation time that is identical whichever of the two pairs of complementary inputs is switched over, whatever the nature of the transition at output and whatever the logic state of the pair of inputs that do not switch over. The disclosed device enables a further reduction in the differences in the time taken for the propagation of the signal edges through the gate by eliminating the floating character of certain nodes. It also relates to a frequency multiplier comprising a tree of Exclusive-Or gates such as this.

Abstract: A process for fabricating a metal-metal capacitor within an integrated circuit comprises the steps of: producing a first metal electrode, a second metal electrode, and a dielectric layer on top of a lower insulating layer; and depositing an upper insulating layer on top of the two metal electrodes and the dielectric layer. The integrated circuit comprises the lower insulating layer, a first metal layer which is on top of the lower insulating layer, and the upper insulating layer which is on top of the first metal layer. The capacitor comprises the first metal electrode, the second metal electrode, and the dielectric layer wherein each of the two metal electrodes is in contact with one side of the dielectric layer. The electrodes and the dielectric layer lie between the lower insulating layer, which supports a level of metallization (M1), and the upper insulating layer which covers this level of metallization.

Abstract: The selector circuit is particularly well suited to the switching over of two voltages VPP1 and VPP2, greater than the supply voltage Vcc of an integrated circuit without a priori knowledge of which of the two voltages is the highest. The selector circuit includes first and second switch circuits coupled by first and second MOS transistors whose well is biased by the output voltage of the selector circuit.

Abstract: A Flash-EPROM type memory cell with a short read time and a "very low supply voltage." The memory cell has the additional advantage of using less power, therefore generating less heat and allowing a denser integrated circuit. The memory cell comprises a floating-gate transistor whose source is coupled to the drain of a selection transistor. The floating-gate transistor is in a depleted state when the memory cell is "erased." The read voltage applied to the control gate of the floating-gate transistor is substantially equal to a general supply voltage which is in the range of 1.5 volts. The gate of the selection transistor receives a bias voltage at least equal to its conduction threshold. The gate of the selection transistor can also receive a bias voltage higher than the read voltage, which will speed up the read time further. A Flash-EPROM incorporating this memory cell is also provided.

Abstract: A current amplifier includes a cascode transistor for fixing the voltage of an input of the amplifier; a first constant current source connected between the input and a first supply voltage; a second constant current source, for providing a current lower than the first current source, connected between a second supply voltage and the cascode transistor; a second transistor, of different type than the cascode transistor, connected between the input and the second supply voltage, and controlled by the node between the cascode transistor and the second current source; and an output transistor of same type as the second transistor, connected to the second supply voltage and controlled by the node.

Abstract: A method for testing output connections of at least one driver circuit that drives a plasma display panel. According to the method, at least one output of the driver circuit is switched to a high level for a predetermined time period. The output of the driver circuit is switched to a low level, and the time to discharge the output of the driver circuit with a constant discharge current is measured. It is determined whether a capacitive load is connected to the output of the driver circuit based on the measured time to discharge. In one preferred method, these steps are repeated for each of the outputs of the driver circuit. A driver circuit for driving a plasma display panel is also provided. The driver circuit includes driver output stages, and means for selectively sinking a constant discharge current from the output of at least one of the driver output stages to ground.

Abstract: An oscillator includes four identical cells each producing a phase shift of 90 degrees. The output signal from one cell is applied to the input of the next cell, and with the cells looping back to themselves. Each cell includes a current amplifier and a parallel inductance-capacitance resonant circuit configured such that the output current from one cell is a fraction of the capacitive current of the parallel resonant circuit. This causes the 90.degree. phase shift between the input and output currents of each cell.

Abstract: In a memory integrated circuit comprising an internal circuit for the generation of a programming high voltage and comprising a first pad designed to receive a main logic supply voltage below five volts, a second specific supply pad is designed to supply the high voltage generation circuit. This enables the application of a specific logic supply voltage with a voltage level greater than that of the main logic supply voltage in test mode or in application mode.

Abstract: An adjustable delay circuit, for a logic input signal, comprises circuitry for charging a capacitance at a first constant current when the logic signal switches to a first logic state; circuitry for discharging the capacitance at a second constant current when the logic signal switches to the second logic state; circuitry for stopping charging and discharging of the capacitance between the moment when the voltage across the capacitance reaches a high threshold or a low threshold and a subsequent switching of the logic signal; and a first comparator connected to switch the state of an output signal when the voltage across the capacitance crosses a third threshold included between the first and second thresholds.

Abstract: A non-isolated voltage converter, of switch-mode type, includes a capacitor between terminals that provide an output voltage regulated by a circuit that controls a switch that provides current to an inductive element. A local supply for the control circuit receives energy from the inductive element. In one embodiment, the inductive element has a tab between two windings, and the output voltage of the converter is smaller than the local supply voltage of the control circuit. In another embodiment, a diode is interposed between a positive terminal of the output capacitor and a positive terminal of a capacitor of the local supply of the control circuit. The negative terminal of the local supply capacitor is connected to the mid-point of a series association of the switch with the inductive element. A zener diode is interposed, in series with the local supply capacitor and the local supply diode, between the mid-point and the positive output terminal.

Abstract: A device for the resetting of a memory circuit in integrated circuit form includes means to recognize a particular sequence on one or more external signals applied to the integrated circuit, different from the sequences of operational functioning of the integrated circuit.

Abstract: The present invention relates to a method of implementing an intermetallic capacitor in a multiple layer integrated circuit including, on a P-type substrate, at least five levels of metallization. The method includes letting remain, on either side of portions of end metallization levels of the capacitor, at least one portion of a biasable level distinct from the substrate and from the last metallization level, and biasing, at least above the capacitor and to the potential of the substrate, the two biasable portions.

Abstract: The present invention relates to a high voltage diode which has a fast turn-off, formed of a series connection of several diodes, the relative intrinsic dispersion of recovered charges between the diodes being smaller than 5%.