Abstract: A semiconductor device includes first through fourth pads and first through third external connection leads, with the first external connection lead being a ground connection lead and the first and second pads being ground pads. First through fourth connection wires selectively connect the pads to the external connection leads. Additionally, a first ground line is connected to the first pad, a second ground line is connected to the second pad, a first protective diode connects the first ground line to the third pad, and a second protective diode connects the second ground line to the fourth pad. The first external connection lead is connected to the first pad via the first connection wire and to the second pad via the second connection wire, the third connection wire connects the third pad to the second external connection lead, and the fourth connection wire connects the fourth pad to the third external connection lead.

Abstract: A semiconductor device includes a chip forming an integrated circuit; a connection substrate; an internal coupling mechanism; and at least one optical communication system. The connection substrate comprises an external coupling mechanism for electrically coupling to a device other than the chip. The internal coupling mechanism electrically couples the integrated circuit to the external coupling mechanism. The at least one optical communication system comprises two optoelectronic parts. The first optoelectronic part is either an emitter or a receiver which is integrated into the chip and constitutes one component of the integrated circuit. The second optoelectronic part is borne by the connection substrate and is able to be externally connected to the connection substrate. The second optoelectronic part faces the first optoelectronic part and is capable of exchanging light signals with the first optoelectronic part.

Abstract: A device including a mechanism (4) for generating a counting clock signal (CKM) whose frequency is less than or equal to n times twice the transmission frequency. The device also includes a detection mechanism (10) for detecting the transitions (TD) of the signal (DS) at the counting frequency and for delivering corresponding detection signals (ST), a selection mechanism (2) for receiving each detection signal (ST) and for delivering or otherwise a selection signal (RS) depending on the satisfying or otherwise of a predetermined selection criterion, and a frequency divider-by-n (30) which receives the counting clock signal, in order to sample the carrier signal after a predetermined time delay (Tr) after each detected transition. Provided are a sampling control device and method which are completely digital and therefore use no analog component of the phase-locked loop type and are very simple to produce at an industrially economical cost.

Abstract: A floating-gate type memory uses voltages that are low in terms of absolute value with a reliable and compact word selection device. The device is compatible with Flash-EEPROM type memories. An N type well transistor is used as a word selection transistor.

Abstract: The present invention relates to a power output stage for the control of plasma screen cells. It includes VDMOS-type N-channel charge and discharge transistors, the charge transistor being arranged to form a compound P-channel transistor. These transistors enable to issue a charge current to an output and to absorb a discharge current from this output. Two inverters are sized so that the potential of the control gate of the charge transistor drops more rapidly than the output potential when a discharge of this output is controlled. Thus, an output stage of limited bulk and without any risk of simultaneous conduction of the charge and discharge transistors is implemented.

Abstract: A device for extracting parameters for decoding a video data flow, contained in headers preceded by a starting code of series of data coded according to an MPEG standard, organized, independently and according to the starting code, and storage of the parameters in three register banks.

Abstract: A method for the testing of the retention time of a piece of information in a dynamic memory cell includes increasing the leakages of current in this cell to accelerate the loss of information. Under these testing conditions, a reduced retention time is controlled to approach the true retention time obtained under conditions of normal reading. This method makes it possible to reduce the time taken to test the retention time of the dynamic memories while at the same time being very reliable.

Abstract: A programmable non-volatile memory device has a plurality of rows of memory cells that are accessible through selection addresses, with the number of physical rows being greater than the number of rows that are addressable at a given time. An associating circuit associates selected physical rows of the memory device with selection addresses. The associating circuit includes an associative memory that has a programmable memory location for each physical row of the memory device, and each memory location in the associative memory has an address field and at least one state bit. In one preferred embodiment, in the read mode, a row of the memory device is selected when the corresponding memory location in the associative memory contains the received address and state bits indicating that the row stores valid data for the received address. A method of programming such a non-volatile memory device is also provided.

Abstract: A memory device includes a defect memory, a test circuit, and a spare memory. The defect memory and the spare memory have as many rows as the array, and each row of the defect memory and the spare memory are selected when the corresponding row of the array is selected. A test circuit locates defective cells of the array and writes addresses in the defect memory to indicate locations of the defective cells. Additionally, a control circuit selects a row of the array based on a selected row address and redirects access to the corresponding row of the spare memory whenever a selected column address corresponds to one of the addresses stored in the defect memory. In one preferred embodiment, each of the rows of the defect memory stores information indicating if there is a defective cell in the corresponding row of the array and the column address of the defective cell. A computer system including such a memory device is also provided.

Abstract: A current-controlled oscillator includes a capacitor, and at least one current source for providing at least one charge current for charging the capacitor. A discharge circuit sequentially discharges the capacitor with a discharge current. A control circuit maintains a mean charge voltage of the capacitor at a preset value by controlling the discharge current. The control circuit includes a current control source forming a current mirror with the at least one current source. The current control source is connected to the discharge circuit for setting the discharge current substantially equal to a sum of the charge currents. The oscillator further includes a correction circuit for correcting the discharge current corresponding to a mean charge of the capacitor.

Abstract: A substitution circuit for elementary flip-flop circuits is provided to enable the automatic transposition of a flip-flop circuit whose clock signal comes from a combinational logic circuit. To do this, an over-sampled internal clock signal is used along with a synchronous pulse generator to validate the data.

Abstract: A device for generating a voltage pulse in a low-voltage integrated circuit includes a capacitor and a control circuit. An input signal having negative pulses is received by the device. The input signal has a high level corresponding to a level of a logic supply voltage for the device, and a low level corresponding to zero volts. The control circuit includes a first and a second circuit element. The first circuit element transmits the low level of the input signal to a second terminal of the capacitor and also provides the capacitor a charging path. The second circuit element transmits the low level of the input signal to a first terminal of the capacitor with a predetermined delay so that a negative pulse between the high level and a negative level is provided at the second terminal of the capacitor in response to the input signal.

Abstract: A method for performing a first programming operation on a non-volatile memory device of the type that is normally programmed by executing a pre-programming erasure algorithm and then a programming algorithm. According to the method, a non-volatile memory device is manufactured with all its memory cells in the same state, and the first programming operation for setting the memory cells to desired states is performed by executing only the programming algorithm. In a preferred method, the memory device is provided with two modes of operation: a first mode in which programming is accomplished by executing the pre-programming erasure algorithm and then the programming algorithm, and a second mode in which programming is accomplished by executing only the programming algorithm. In the preferred method, the memory device is placed in the second mode of operation before the first programming operation is performed. A non-volatile memory device having two modes of operation is also provided.

Abstract: A process for manufacturing semiconductor packages comprising, respectively, a substrate, a chip which forms an integrated circuit and is attached to one region of the substrate, electrical connection means connecting the chip to a group of external electrical connection regions lying on one face of the substrate, as well as an encapsulation encasement. The process consists in producing, in a matrix configuration, a multiplicity of groups of connection regions (104a) on a common substrate plate (102), corresponding to as many chip attachment regions (109), in attaching a chip (103) to each attachment region (109) of the common substrate plate, in electrically connecting each chip (103) to the associated electrical connection regions (104a), so as to obtain an assembly (111) consisting of the substrate plate and the connected chips.

Abstract: An electrical connection device for electrically connecting an electronic component of the type having electrical connection points. The electrical connection device includes electrical connection members that each have a tip that can retract against an elastic means, a support carrying the electrical connection members, and a movable receptacle. The movable receptacle can house an electronic component and can bring the electronic component into a connection position in which the tips of the electrical connection members bear on the electrical connection points of the electronic component. In a preferred embodiment, the electrical connection members are removable from the device. Additionally, a testing apparatus that includes such an electrical connection device is provided.

Abstract: A semiconductor device having separated exchange mechanism comprises a chip forming an integrated circuit; a connection substrate; device connection points or balls; and at least one exchange mechanism. The connection substrate comprises an external connection mechanism. The device connection points or balls are distributed in the form of a matrix and are located between the juxtaposed faces of the chip and of the connection substrate. The device connection points are connected to the external connection mechanism. The exchange mechanism comprises two parts. The two parts are arranged so as to be separated from each other and capable of exchanging signals between each other, in one or both directions. The first part is physically coupled to the chip. The second part is physically coupled to the connection substrate and is connected to the external connection mechanism.

Abstract: The method is for the control of an electrical oven and includes taking into account the temperature and/or the humidity level of the air measured by sensors in the interior of a cavity of an oven in which food to be heated and/or cooked is placed. The instantaneous value of the supplied power of the magnetron of the oven and the duration of a heating cycle are controlled, such as by fuzzy logic.

Abstract: The present invention relates to a buffer for logic signals including a MOS output transistor of a first conductivity type connected by its source to a first supply potential, the drain of this transistor forming an output terminal of the buffer; a control transistor for controlling the output transistor connected between the gate of the output transistor and a second supply potential; a third transistor of the first conductivity type connected between the gate of the output transistor and the first supply potential and controlled to maintain the gate-source voltage of the buffer close to a threshold voltage so that the output transistor operates as a current generator; and a fourth transistor connected to render floating the gate of the third transistor when the potential on the output terminal is close to the first supply potential.

Abstract: A method of manufacturing a bipolar transistor in an integrated circuit including the steps of forming a P-type base area, coating this base area with an isolating layer, and forming an opening in the isolating layer at a location where it is desired to form the emitter region. The method further includes coating the structure with an N-type doped polysilicon layer, etching the polysilicon layer to delimit a portion therefrom, forming spacers at a periphery of the polysilicon portion, and implanting a P-type dopant to form a base contact making region, after masking the polysilicon portion, above the area where it is in contact with the base area.

Abstract: A relaxation oscillator includes a first capacitor at the terminals of which there is a first voltage V.sub.1, a circuit to charge the first capacitor from a power supply voltage, a circuit to discharge the first capacitor, and a switch which alternately charges and discharges the first capacitor responsive to a control signal. The relaxation oscillator also includes a relaxation circuit to generate the oscillation signal and the control signal from the first voltage. The oscillator also includes a regulation circuit to cause the first voltage applied to the relaxation circuit to be approximately equal to a reference voltage. The circuit for charging the first capacitor includes a resistance R.sub.1. The relaxation oscillator is particularly applicable to phase locked loops.