Abstract: The present invention relates to a constant current generator including a reference voltage source providing a constant voltage with respect to a first ground; an operational amplifier receiving the constant voltage on a non-inverting input; and a follower transistor controlled by the output of the operational amplifier and connected between an input of a current mirror and a first resistor connected to the first ground. It further includes a second resistor connected between an output of the current mirror and a second ground, the output of the current mirror being also coupled to an inverting input of the operational amplifier; and a filtering circuit connected to reduce or eliminate, in the output signal of the operational amplifier, any high frequency ac component with respect to the first ground.

Abstract: The present invention relate to a device of protection against voltage gradients of a monolithic component including a vertical MOS power transistor and logic circuits. The protection circuit has an N-type substrate corresponding to the drain of the MOS transistor, and logic components being realized in at least one P-type well formed in the upper surface of the substrate. Each of the N-type regions connected to the ground of the logic circuit, or to a node of low impedance with respect to the ground, is in series with a resistor.

Abstract: The present invention relates to a protection device for a component including a vertical MOS power transistor and logic components. The protection device includes a first zener diode, a first terminal of which corresponds to the substrate and a second terminal of which corresponds to a region of the second type of conductivity formed in the substrate. It also includes a second zener diode of the same type of conductivity as the first zener diode but of higher avalanche voltage, the second terminals of both zener diodes being connected to a circuit for starting the power transistor via a logic circuit which only becomes conductive when one of its inputs is high and distinct from the other input.

Abstract: The present invention relates to a Vbe/R bias source of the type including a first reference branch, a second output branch, and means of correction of an output current by an error current proportional to the current flowing in the reference branch.

Abstract: The present invention relates to a component protecting against electric overloads likely to occur on a conductor in series with which is placed a detection resistor. The component includes a first cathode-gate thyristor and a second anode-gate thyristor, of the gate current or forward break-over type. The anode region of the first thyristor, formed on the lower surface side, is separate from the isolating wall surrounding the thyristor and the rear surface of the isolating wall is coated with a portion of an insulating layer.

Abstract: A power supply device for a non-linear load, especially a magnetron for microwave ovens, includes a resonant transformer. Using a fuzzy logic management unit, a level of a low voltage signal on the primary side of the transformer, a level of high voltage signal on the secondary side of the transformer, and a signal corresponding to the ambient temperature of the transformer are taken into account for the generation of a parameter for a control signal for controlling a switch positioned at the primary winding of the transformer. The power supply device makes it possible to reduce the size of the resonant transformer.

Abstract: The reading of a reference memory slot placed outside the memory plane is detected by comparing the voltage difference at the terminals of one of the two bit lines of the additional column with VDD/2. Only the read amplifiers of the memory are then activated.

Abstract: A method for writing in an electrically erasable and programmable non-volatile memory (EEPROM, Flash EEPROM) includes keeping a gate of a selection transistor at its maximum value for the erasure or programming of a memory cell, so long as the potential at a drain or source of the transistor is not zero or at a very low level. This increases the lifetime of the selection transistors.

Abstract: A process is for controlling a memory-plane refresh of a dynamic random-access memory. After having selected at least one first reference memory cell structurally similar to the memory cells of the memory plane, to store a first predetermined binary information item therein, the voltage across the terminals of the storage capacitor of this first reference memory cell is compared with a first predetermined reference voltage. When the voltage reaches the reference voltage, a control signal is delivered in response to which the memory plane is refreshed, then the first reference memory cell is again selected in order to refresh its contents.

Abstract: An electrically erasable and programmable non-volatile semiconductor memory includes memory registers that are addressable individually or by blocks. The memory also has a protection register in which a protection word can be written. The protection word has a given number of bits that encode a boundary address of the memory register or a block of memory registers. The boundary address divides the memory space into an upper zone and a lower zone. The protection word also has a zone bit whose value determines which of the two zones of the memory is to be write protectable.

Abstract: An antenna coil with low electrical field emissions comprises a flat winding with a specified shape and a conductive screen facing the winding. The conductive screen has substantially the same shape as the winding, and includes a cut-off zone. The screen neutralizes the parasitic electrical field emitted by the winding without disturbing the useful magnetic field which is axially oriented (i.e., oriented perpendicularly to the plane of the coil). Such an antenna coil is applicable to a station for the transmission-reception of data by inductive coupling.

Abstract: A contactless chip card, receiving binary data transmitted by radio frequency, includes a demodulator for the binary data. The demodulator includes a circuit for the detection of the transmitted signals, a rectifier circuit, a bandpass filter, two comparators and a memory circuit. The bandpass filter provides a low-frequency signal used as a reference for the two comparators and a high-frequency signal that is compared with the references varying with the low frequency signal. As a result, the demodulation is independent of the mean level of the received signal.

Abstract: A invention provides a transformer for use in integrated circuits, comprising four layers of conductive lines, separated from each other by first, second and third insulating layers. First conductive vias traverse the second insulating layer to connect said second and third pluralities of conducting lines, to form a first winding. Second conductive vias traverse the first, second and third insulating layers to connect said first and fourth pluralities of conducting lines to form a second winding, about and approximately concentric with said first winding.

Abstract: A dual gain amplifier provides separate gains so that the amplifier's input characteristics are unaffected by the gain selected. The dual gain amplifier comprises a first input amplifier and a third amplifier connected in cascade, and a second input amplifier and a fourth amplifier connected in cascade. A first LC circuit is connected in parallel to a second LC circuit which are both connected to the third amplifier. Likewise, a third LC circuit is connected in parallel to a fourth LC circuit which are connected to the fourth amplifier. The first and third LC circuits have a first quality factor and the second and fourth LC circuits have a second quality factor. The dual gain amplifier switches from a first state in which only the first and third LC circuits conduct to a second state in which all four LC circuits conduct.

Abstract: The present invention relates to the use of a conventional MOS transistor as a memory point in which, during programming, the well of the MOS transistor is connected to a reference potential, the drain and the source are connected to a current source adapted to bias the drain and source junctions in reverse and in avalanche so that the space charge region extends along the entire channel length, the gate is set to the reference potential if the memory point does not have to be programmed and to a distinct potential if the memory point has to be programmed; and during the reading, circuitry is provided to detect a high or low impedance state between the gate and the well.

Abstract: An EEPROM is organized in matrix form in word lines and bit lines. Storage cells are placed at the intersections of these lines. The cells include floating gate storage transistors. Groups of cells having separate bit lines but sharing a word line are created. Each group is connected to a group selection transistor. The group selection transistor selectively connects the control gates of the storage transistors to control lines, which provide potentials for enabling programming, erasure or reading of the storage transistors.

Abstract: The start-up aid circuit is connected to a plurality of current sources. The start-up aid circuit is common to all the current sources and supplies a start-up current to each current sources when the current sources are operating in a transient operating state following power-up of the apparatus. The circuit also inhibits the start-up aid circuit when all the current sources have reached an operating state described as stationary. The circuit may be applied to the power supply of microprocessors and electronic equipment.

Abstract: A dynamic random access memory device with reduced refresh duration, and corresponding refresh process includes a plurality of memory cells. All of the memory cells of one and the same column are connected between two column metallizations, and each comprise four insulated-gate field-effect transistors. The four transistors include two storage transistors both possessing the same first quotient of their channel width to their channel length. The four transistors also include two access transistors both possessing the same second quotient of their channel width to their channel length. The ratio of the first quotient to the second quotient is greater than or equal to one. The ratio of the capacitance of a column metallization and the gate/source capacitance of each storage transistor is at least equal to 50. During a specific refresh cycle, several memory cells of one and the same column are selected simultaneously.

Abstract: The present invention relates to various methods and apparatus for obtaining a parameter J.sub.0 that is used in modular computations using the Montgomery method. The parameter J.sub.0 is defined by the formula (J.sub.0 *N.sub.0 +1)mod 2.sup.Bt =0, Bt being the working base in which the Montgomery method is carried out, and N.sub.0 being the Bt least significant bits of a modulo N used in the Montgomery method.

Abstract: A control and monitoring circuit for a power switch comprises a first portion (20) connected to this switch and fed with reference to a floating voltage (V.sub.F) of an electrode of this switch, a second portion (10) connected to circuits external to the switch and fed with reference to a fixed voltage, a coder (40) arranged on the side of the second portion and a suitable decoder (50) arranged on the side of the first portion.