Abstract: A security system of the type having a fixed terminal and a portable unit such as a remote control. The portable unit produces an activation signal based on active intervention by a user and a measurement signal based on the measurement of a biometrical signature of the user. A control signal is generated when the activation and measurement signals are both generated within a specified temporal window and the measured biometrical signature corresponds to that of an authorized user. Thus, there is a reduced chance of both the security system being disarmed by an ill-intentioned third party and of untimely or inadvertently disarming the system.

Abstract: A semiconductor test structure includes a semiconductor test device having at least one group of test cells that are connected in series and looped back so as to form an oscillator. Each test cell includes a base cell that is formed at least partially in the semiconductor substrate and an ancillary structure that is connected to at least one of the terminals of the base cell. Further, the ancillary structure is distributed over at least two metallization levels that are above the base cell, and is formed on each metallization level by first and second mutually entangled networks of metal tracks that are electrically arranged so as to form an at least capacitive ancillary structure.

Abstract: The present invention relates to a method of deposition of a silicon layer on a single-crystal silicon substrate 11 , so that the silicon layer is a single-crystal layer, but of different orientation than the substrate, including the steps of defining a window 13 on the substrate; creating inside the window interstitial defects 14 with an atomic proportion lower than one for one hundred; and performing a silicon deposition 15 in conditions generally corresponding to those of an epitaxial deposition, but at a temperature lower than 750.degree. C.

Abstract: The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.

Abstract: A low supply voltage comparator in BICMOS technology includes: a first stage (1) with differential inputs (2,3) including, among others, two MOS transistors (MP1, MP2) of a first channel type controlling a first output bipolar transistor (T's); a second stage with differential inputs (2, 3) including, among others, two MOS transistors (MN1, MN2 (of a second channel type controlling a second output bipolar transistor (T's), the output transistors being mounted in series between two (A, M) terminals of application of respectively positive (Vdd) and negative (Vss) supply voltages; a switch (13' 13') for selecting one of the output transistors according to the common mode level of the input voltages with respect to the supply voltages; and a controller (15) for controlling the switch in all or nothing.

Abstract: The present invention relates to a composite integrated circuit including at least one well that separates analog and digital blocks of the circuit, this well being connected to a first terminal of a power supply of biasing of one of the two blocks, and being of type opposite to that of the circuit substrate, and a resistor being interposed on the well biasing link.

Abstract: A device for generating a high voltage includes a charge pump device that outputs a high voltage, an oscillator that supplies at least one clock signal to the charge pump device, and a regulation device. The regulation device generates a control signal to selectively stop the charge pump device based on the level of the high voltage output by the charge pump device. Additionally, the oscillator includes a shaping circuit for shaping the clock signal into a saw-tooth waveform. In a preferred embodiment, the oscillator supplies at least two clock signals to the charge pump device, and each of the clock signals has a saw-tooth waveform. A method for generating a high voltage in an integrated circuit is also provided. According to the method, at least one clock signal is generated, and the clock signal is shaped into a saw-tooth waveform. The shaped clock signal is used to generate a high voltage, and the generation of the high voltage is selectively stopped based on the level of the high voltage.

Abstract: A method for the repairing of defective elements of a memory in integrated circuit form, comprising redundant elements to replace defective elements, consists of the following steps:A) For each defective element detected:searching for a first non-defective redundant element by the testing of the redundant elements;assigning this first redundant element to the defective element.B) When the assigning of a redundant element to each defective element has been achieved, replacing each defective element by the assigned redundant element.

Abstract: The present invention relates to a method of manufacturing, in a P-type substrate including active areas separated by field oxide areas, heavily-doped stop-channel regions under portions of the field insulation areas, more lightly-doped P- and N-type areas meant to form MOS transistor wells, and heavily-doped N-type areas meant to form the first electrode of a capacitor, including the steps of performing a high energy N-type implantation in P-channel MOS transistor areas; performing a high energy P-type implantation in N-channel MOS transistor areas; performing a high energy P-type implantation in stop-channel areas and in capacitor areas; and performing a low energy N-type implantation, masked by the field oxide.

Abstract: A contactless chip card includes a circuit for detecting the presence of radio frequency signals. A detector comprises at least one circuit for detecting the presence of radio signals by making direct use of the corresponding signals received by an antenna winding. In addition, a phase-shift detector detects the relative phase differences between signals provided by the antenna winding.

Abstract: A device for the protection of an integrated circuit input/output pin against electrostatic discharges includes a first diode between a positive power supply line and an internal connection node for connection to the pin, and a second diode between the internal node and a second negative or zero supply line. The device also includes a protection transistor series-connected between the positive power supply line and the first diode, and a stack of N diodes, where N is equal to one or more, series-connected between the control electrode of the protection transistor and the first diode.

Abstract: A voltage converter includes a resonant element and a switch controlled by a management unit for regulating a quantity of energy transferred from the primary circuit to the secondary circuit. The voltage converter includes a circuit for generating the supply voltage for the management unit from the output voltage of the voltage converter, and a circuit for holding the switch in a closed position when the voltage converter is initialized.

Abstract: The present invention relates to a method of manufacturing a JFET transistor in an integrated circuit containing complementary MOS transistors, this JFET transistor being formed in an N-type well of a P-type substrate, including the steps of forming a P-type channel region at the same time as lightly-doped drain/source regions of the P-channel MOS transistors of; forming an N-type gate region at the same time as lightly-doped drain/source regions of the N-channel MOS transistors; and forming P-type drain/source regions at the same time as heavily-doped drain/source regions of P-channel MOS transistors of channel.

Abstract: An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

Abstract: A system of regulation of a charge pump for providing an overvoltage greater by a predetermined amount than a supply voltage, including a constant current source connected between the supply voltage and a control terminal, an N-channel MOS transistor connected between the control terminal and the ground, the gate of which is connected to receive the overvoltage, the transistor being of such dimensions that it conducts all the current provided by the constant current source when the overvoltage is greater than a maximum allowable voltage, and circuitry for limiting the overvoltage when the voltage of the control terminal is close to the ground potential.

Abstract: A method for positioning/routing a clock circuit for an integrated circuit compensates for phase differences by adjusting secondary amplifiers having adjustable input delays. The method includes the steps of positioning first conductive lines parallel to a first direction evenly spaced with respect to the second direction. The first conductive lines are connected to outputs of the first amplifiers. A balanced tree-like structure provides each of the first amplifiers a clock signal coming from a single source. The method further includes the steps of positioning functional blocks for forming the integrated circuit, and the positioning of second lines parallel to the second direction. Each secondary amplifier is routed to the closest second line. An equivalent electrical diagram corresponding to the path taken by the clock signal between the input of the tree-like structure device and the input of each secondary amplifier is determined.

Abstract: The SECAM chrominance signal demodulator includes an oscillator with a controlled frequency, a phase comparator with a first input connected to an oscillator output, a second input to receive a chrominance signal, and an output connected to an input loop of the oscillator. The demodulator further includes a fixed current source, also connected to the loop input, a current mirror to copy a current equal to the sum of the fixed current and a comparator output current in the output branches comprising first and second calibration resistors respectively, in series with a common resistor. Output voltages corresponding to the red and blue components of the chrominance signal are measured at the terminals of the calibration resistors respectively. The demodulator is used in television sets, for example.

Abstract: A chip card reader may be connected to a microcomputer to provide for data exchanges in the read or write mode between the card and the microcomputer, under the control of the microcomputer. The reader is capable of carrying out data exchanges between the card and the microcomputer and works without a microprocessor. The chip card reader is provided, firstly, with a data buffer memory enabling the temporary storage of the pieces of data read in the card, and, secondly, with a frequency divider programmable by a frequency signal to set the bit time at will. By the division of frequency of an internal clock of the reader, this bit time is the duration corresponding to the transmission of a data bit in the data exchanges between the chip card and the reader. The reader can then carry out transmissions with slow or fast protocols independently of the microcomputer.

Abstract: The present invention relates to a voltage regulator of a voltage meant to supply a load from a battery, including a first switched-mode power supply type voltage regulation component, a second linear regulator type voltage regulation component, and a control circuit that selects one of the two regulation components according to the voltage difference between the battery voltage and the output voltage.

Abstract: A structure for protection against electrostatic surges having two input terminals and two output terminals. The output terminals of the structure are connected to the inputs of a circuit to be protected. A first input terminal is connected to a first output terminal via an impedance. The second input terminal is connected to the second output terminal. The input terminals are interconnected by a first avalanche diode. The output terminals are interconnected by a second avalanche diode having the same biasing as the first avalanche diode.