Patents Assigned to STMicroelectronics S.A.
  • Temperature-compensated current source
    Publication number: 20030132796
    Abstract: A temperature-compensated current source includes a first arm fixing a reference voltage, a second arm fixing a reference current, and a third arm providing an output current obtained by copying the reference current in a first current mirror. A second current mirror copies, in the voltage reference arm, the reference current while a voltage copying circuit copies the reference voltage at a node of the second arm connected to ground by a first resistor series-connected with n parallel-connected diodes. A second resistor is parallel-connected with the assembly formed by the first resistor series-connected with the n parallel-connected diodes.
    Type: Application
    Filed: November 25, 2002
    Publication date: July 17, 2003
    Applicant: STMicroelectronics S.A.
    Inventors: Bruno Gailhard, Olivier Ferrand
  • Flash memory including means of checking memory cell threshold voltages
    Publication number: 20030133344
    Abstract: A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.
    Type: Application
    Filed: January 28, 2003
    Publication date: July 17, 2003
    Applicant: STMicroelectronics S.A.
    Inventors: Paola Cavaleri, Bruno Leconte, Sebastien Zink, Jean Devin
  • Responsive bidirectional static switch
    Patent number: 6593600
    Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of type N, including a first main vertical thyristor, the rear surface layer of which is of type P, a second main vertical thyristor, the rear surface layer of which is of type N, an auxiliary vertical thyristor, the rear surface layer of which is of type P and is common with that of the first main thyristor, a peripheral region of type P especially connecting the rear surface layer of the auxiliary thyristor to the layer of this thyristor located on the other side of the substrate, a first metallization on the rear surface side, a second metallization on the front surface side connecting the front surface layers of the first and second thyristors. An additional region has a function of isolating the rear surface of the auxiliary thyristor and the first metallization.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: July 15, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Franck Duclos, Jean-Michel Simonnet, Olivier Ladiray
  • Multiplexed flip-flop electronic device
    Patent number: 6593777
    Abstract: A multiplexed flip-flop electronic device includes a decoder logic circuit for providing a first switching signal, and a control circuit for receiving a clock signal and for providing a gated clock signal forming a second switching signal. The electronic device further includes a multiplexing circuit having N inputs and an output, and a flip flop circuit. The flip-flop circuit includes a first switching stage connected between the N inputs and the output of the multiplexing circuit, and includes N switches being individually controlled by the first switching signal. A first buffer stage is connected to the output of the multiplexing circuit, and a second switching stage is connected to an output of the first buffer stage. The second switching stage is controlled by the second switching signal. A second buffer stage is connected to an output of the second switching stage.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: July 15, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Thomas Alofs
  • Frequency transposition device having low local oscillator signal leakage and corresponding leakage reduction process
    Patent number: 6594504
    Abstract: The residual quantity of a local oscillator signal in the output signal from a frequency transposition device having a differential Gilbert type structure is reduced by biasing the transistors of the output stage of the differential transconductor block of the device. The biasing is performed by carrying out differential slaving of the conduction terminal of these transistors to a predetermined common mode current.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: July 15, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Jean-Charles Grasset
  • Vertical power component manufacturing method
    Publication number: 20030129812
    Abstract: A method for manufacturing a vertical power component on a silicon wafer, including the steps of growing a lightly-doped epitaxial layer of a second conductivity type on the upper surface of a heavily-doped substrate of a first conductivity type, the epitaxial layer having a thickness adapted to withstanding the maximum voltage likely to be applied to the power component during its operation; and delimiting in the wafer an area corresponding to at least one power component by an isolating wall formed by etching a trench through the epitaxial layer and diffusing from this trench a dopant of the first conductivity type of high doping level.
    Type: Application
    Filed: January 17, 2003
    Publication date: July 10, 2003
    Applicant: STMicroelectronics S.A.
    Inventors: Gerard Auriel, Laurent Cornibert
  • Bidirectional flip-flop
    Patent number: 6590349
    Abstract: A bidirectional switch, including a first bidirectional switch between two power terminals of the switch, a low-voltage storage element between a first power terminal and a control terminal of the switch, and a control stage adapted to cause, upon each halfwave beginning of an A.C. supply voltage applied between the power terminals and when the switch is on, the charge of the storage element with a biasing depending on the sign of the halfwave.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: July 8, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Laurent Moindron
  • Current source able to operate at low supply voltage and with quasi-null current variation in relation to the supply voltage
    Patent number: 6590371
    Abstract: A current source includes a current mirror and a core connected together between two supply terminals. The current mirror comprises a pilot transistor and first and second recopy transistors. The core comprises first and second transistors and a resistance. The first transistor and the first recopy transistor are connected together to form a first branch. The resistance and the second recopy transistor are connected together to form a second branch. The pilot transistor and the second transistor are connected together to form a third branch. These branches are connected between the two supply terminals. The first transistor is linked to the second branch between the resistance and the second recopy transistor. The second transistor is connected to the first branch between the first core transistor and the first recopy transistor.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: July 8, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Philippe Sirito-Olivier
  • EEPROM cell testing circuit
    Patent number: 6590256
    Abstract: A testing circuit made on a silicon wafer including a plurality of identical cells, each of which includes a primary capacitor of given characteristics, which includes a test capacitor of same characteristics as each primary capacitor and of surface at least equal to the sum of the surfaces of the primary capacitors.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: July 8, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Philippe Boivin
  • Memory cells incorporating a buffer circuit and memory comprising such a memory cell
    Patent number: 6590812
    Abstract: A memory cell is formed with a buffer circuit. The output of the buffer circuit is linked to the input to form a logic latch. A write-access transistor is disposed between a first node linked to a bit line and the input of the buffer circuit. A control gate of the write-access transistor is linked to a second node linked to a write word line, and a read-access transistor is disposed between the first node linked to the bit line and a third node linked to a read word line. A control gate of the read-access transistor is linked to the output of the buffer circuit.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: July 8, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Christophe Frey
  • Device for the control of a circuit for the vertical deflection of a spot scanning a screen
    Patent number: 6590353
    Abstract: Disclosed is a device to control a circuit for the vertical deflection of a spot scanning a screen, and more particularly a control device whose output amplifier stage works in class D mode at the rate of a switching signal called a first switching signal. The control device has an internal auxiliary supply to generate the overvoltage needed for the fast flyback of the spot. This auxiliary power supply is a switching voltage generation circuit whose switching signal, called a second switching signal, is synchronous with the first switching signal. The present invention has been shown to used advantageously in television screens and/or computer screens.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: July 8, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Philippe Maige, Yannick Guedon
  • Method and apparatus for regulating output voltage of a voltage converter
    Patent number: 6590789
    Abstract: A voltage converter including a circuit for controlling a switch for providing current to a primary winding of a transformer with inverted phase points, a secondary winding of which is associated with a capacitor for providing a regulated D.C. output voltage and an auxiliary winding of which provides a supply voltage of the control circuit. The average value of the voltage across the auxiliary winding close to the end of its demagnetization periods.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: July 8, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Alain Bailly
  • Method of manufacturing unipolar components
    Patent number: 6590240
    Abstract: A method of manufacturing a unipolar component of vertical type in a substrate of a first conductivity type, including the steps of: forming trenches in a silicon layer of the first conductivity type; coating the lateral walls of the trenches with a silicon oxide layer; filling the trenches with polysilicon of the second conductivity type; and annealing to adjust the doping level of the polysilicon, the excess dopants being absorbed by the silicon oxide layer.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: July 8, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Frédéric Lanois
  • Semiconductor package with a sensor having a fastening insert
    Publication number: 20030122249
    Abstract: A semiconductor package is provided that includes an electrical connection and support means having a front face and a recess in the front face. The semiconductor package also includes a semiconductor component having a front face including a sensor and a rear face which presses on the bottom of the recess of the electrical connection and support means. Further included in the semiconductor package is a positioning and locking means for locking the semiconductor component onto the electrical connection and support means. The positioning and locking means is engaged in a space which separates the periphery of the semiconductor component from the periphery of the recess and keeps the semiconductor component pressed against the bottom of the recess. Thus, there is provided a semiconductor package having efficiently oriented components.
    Type: Application
    Filed: November 14, 2002
    Publication date: July 3, 2003
    Applicant: STMICROELECTRONICS S.A.
    Inventor: Christophe Prior
  • Process and device for evaluating symbol lengths on a recording medium
    Publication number: 20030123362
    Abstract: A symbol length is evaluated on the basis of receiving a first-symbol length, and a phase error with respect to detection of a length of the first symbol before receiving a length of a second symbol following the first symbol. The process includes evaluating at least two random phase errors on the basis of the phase error received. A first random phase error is dependent on a deterministic phase error with respect to a first state corresponding to an absence of a corrected first-symbol length. A second random phase error is dependent on a deterministic phase error with respect to a second state corresponding to the corrected first-symbol length. The process includes retaining as an evaluated symbol length the first-symbol length received if the absolute value of the first random phase error reduces a condition of passing through the first state.
    Type: Application
    Filed: December 16, 2002
    Publication date: July 3, 2003
    Applicant: STMicroelectronics S.A.
    Inventor: Philippe Graffouliere
  • Secure EEPROM memory comprising an error correction circuit
    Publication number: 20030126513
    Abstract: An electrically erasable and programmable memory includes at least one non-erasable secured zone. Detection and/or correction of read errors in the secured zone is provided by recording redundant bits in the secured zone and delivering an error signal and/or a bit having the majority value when the redundant bits read in the secured zone are not equal.
    Type: Application
    Filed: December 11, 2002
    Publication date: July 3, 2003
    Applicant: STMicroelectronics S.A.
    Inventor: Sylvie Wuidart
  • Switched mode power supply device adapted for low current drains, and cellular phone equipped with such a device
    Publication number: 20030122531
    Abstract: A switched mode power supply device comprising a power transistor periodically set to conduction and supplying a regulated voltage that comprises a ramp generation circuit controlled by a clock signal and periodically generating a ramp voltage. The device includes an amplifier error circuit between a reference voltage and said regulated output voltage and generates an error signal, and a comparator comparing the ramp voltage with said error voltage and providing an output signal for controlling said power circuit. The circuit is characterized in that it comprises a delay element delaying the setting to conduction of the power transistor so as to desynchronize the starting of the ramp and said setting to conduction.
    Type: Application
    Filed: September 6, 2002
    Publication date: July 3, 2003
    Applicant: STMicroelectronics S.A.
    Inventors: Jerome Nebon, Alexandre Balmefrezol
  • Processor and system for controlling shared access to a memory
    Patent number: 6587932
    Abstract: Several peripheral entities, each of which is clocked by its own internal clock signal, can access a memory that is a single-access memory. A priority entity is defined from among the peripheral entities, and the other entities are defined as auxiliary entities. A repetitive time frame is formulated so as to be regulated by the internal clock signal of the priority entity. This time frame is subdivided into several groups of windows that are allocated to the peripheral entities. Each peripheral entity can access the memory only during the windows that are allocated to that entity.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: July 1, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Christian Tournier
  • Structure and method of repair of integrated circuits
    Patent number: 6586961
    Abstract: The present invention relates to an integrated circuit, at least one portion of which includes at least one group of standby cells for possible connection to said portion of the integrated circuit by replacement connections, the length of which cannot exceed a predetermined value. The inputs and outputs of the standby cells are connected to metal standby tracks being disposed on the circuit such that any node of the circuit portion is distant by at most said predetermined value from any point on the tracks.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: July 1, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Philippe Chaisemartin
  • Low cost digital FM modulator
    Patent number: 6587011
    Abstract: A modulator including a noise shaper receiving the input signal and providing a signal coded over one bit, a phase loop including an adder and a shift register. The adder receives the signal coded over one bit, the output of the shift register, and a constant. The input of the shift register receives the adder output. A sinusoidal shaper is coupled to the output of the shift register to provide a signal modulated in frequency by the input signal. The present invention also relates to a modulation chain including a modulator.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: July 1, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Pascal Mellot