Abstract: A pointing device for a computer system includes a displacement transducer of the pointing device, provided with: an inertial sensor, supplying acceleration signals indicative of an acceleration according to two axes of detection; and a processing unit, which, on the basis of the acceleration signals, generates velocity signals regarding the pointing device. The processing unit further includes: a state-recognition stage, for selectively recognizing a condition rest and a motion condition of the pointing device on the basis of the velocity signals; and an estimating module, controlled by the state-recognition stage for determining an estimate of stationary disturbance contained in the acceleration signals when the pointing device is in the rest condition.

Abstract: A memory cell includes a memory element and a selection element coupled to said memory element. The selection element includes a first junction portion, having a first type of conductivity, and a second junction portion, having a second type of conductivity and forming a rectifying junction with the first junction portion. The first junction portion and the second junction portion are made of materials selected in the group consisting of: chalcogenides and conducting polymers.

Abstract: A non-volatile memory device includes a chip of semiconductor material. The chip includes a memory and control means for performing a programming operation, an erasing operation and a reading operation on the memory in response to corresponding external commands. The chip further includes testing means for performing at least one test process including the repetition of at least one of said operations by the control means, and a single access element for enabling the testing means.

Abstract: A current sense amplifier, in particular for low voltage applications, of the type incorporated in a memory electronic device and including a differential amplifier having inputs respectively associated with a matrix circuit leg, connected to a cell to be sensed, and a reference circuit leg, connected a reference cell. At least the matrix circuit leg has a first MOS transistor to which an inverter is connected in a cascode configuration and a first input of the differential amplifier corresponding to the matrix circuit leg is coupled to a conduction terminal of the first MOS transistor and to the bitline of the memory matrix by a second MOS transistor.

Abstract: A method controls write/erase operations in a memory device, such as a NAND flash memory. The method includes dividing the memory device in physical blocks, wherein each physical block is comprised of a number of pages; considering the memory device as comprising consecutive virtual blocks, each virtual block including consecutive sectors; associating to each virtual block a virtual block number; selecting the size of the virtual blocks equal to a multiple of the size of the physical blocks; and creating a virtual-to-physical mapping table having entries. Each entry in the mapping table stores a pointer to a root node of a tree structure that links logically a set of physical blocks in the memory device.

Abstract: A single-stage clock booster produces a boosted clock voltage on an output node that is a multiple of a supply voltage. The single-stage clock booster includes a pump capacitor having a first terminal being driven by a first control phase signal. A first switch is controlled by the boosted clock voltage for connecting a second terminal of the pump capacitor to the supply voltage during a charge phase. A second switch connects the second terminal of the pump capacitor to the output node during a boosted clock voltage output phase. A switching circuit alternately connects a control node of the second switch to the supply voltage and to the first terminal of the pump capacitor. The switching circuit is driven by a second control phase signal. A third switch is controlled by a third control phase signal for connecting the output node to a reference voltage during the charge phase.

Abstract: A Design Failure Mode Effect Analysis (DFMEA) method analyzes faults and failures in the design phase of electronic devices. A data-entry mask is used for recording some information concerning the performed analysis and a portion of the recording form is displayed to a user in an electronic display format. The method detects and records past design problems and their corresponding solutions, by a DFMEA method using the data-entry mask form; associates keywords in a database with each problem; associates data concerning each of the design problems, in the same database, including information concerning past fails occurred in similar applications; detects major changes and/or innovations, as well as any improved block or part of a new device with respect to other devices, thereby postulating possible new problems introduced by the new device; and records the new problems and their possible solutions, by the DFMEA method and using the form.

Abstract: In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a predetermined resistivity is then formed in the active area (15). Prior to forming the resistive region (21), however, a delimitation structure (20) for delimiting the resistive region (21) is obtained on top of the active area (15). Subsequently, protective elements (25) are obtained which extend within the delimitation structure (20) and coat the resistive region (21).

Abstract: In order to speed up the search for a data item in a content addressable memory and to simplify the circuit structure of the memory having associated with each row of cells a ground control line, a ground line, a match control line, and with every row of cells there is associated a search activation terminal and a match indication terminal; a method of controlling the storage and retrieval of data in the memory utilizing a unique comparison strategy for determining when the content of a comparison register is found in the memory.

Abstract: The method for manufacturing a micromechanical switch includes manufacturing a hanging bar, on a first semiconductor substrate, equipped at an end thereof with a contact electrode, and a frame projecting from the first semiconductor substrate. A second semiconductor substrate with conductive tracks includes a second input/output electrode and a third starting electrode, and first and second spacers electrically connected to the conductive tracks. The frame is abutted with the first spacers so that the fourth contact electrode abuts on the second input/output electrode in response to an electrical signal provided to the hanging bar by the third starting electrode.

Abstract: A control circuit is for an electric power plant including an asynchronous generator of an AC voltage, a motor to rotate a rotor of the asynchronous generator as a function of a first control signal of a developed motor torque, and a bank of capacitors coupled to the asynchronous generator and having a total capacitance varying as function of a second control signal. The control circuit may include a monitor circuit to monitor at least one parameter of the AC voltage, and a control signal generator circuit cooperating with the monitor circuit to generate the first and second control signals by soft-computing techniques both as a function of the frequency and of a representative value of an amplitude of the AC voltage to make the AC voltage have a desired amplitude and frequency.

Abstract: A method and circuit for programming a multilevel memory of a flash EEPROM type having a matrix of cells grouped in memory words. The method provides for the simultaneous generation of a first programming voltage value and a second verify voltage value to bias word lines of the memory matrix during programming and verify operations, respectively, of the memory itself. A circuit implementing the above method is also provided.

Abstract: A crosspoint memory includes a shared address line. The shared address line may be coupled to cells above and below the address line in one embodiment. Voltage biasing may be utilized to select one cell, and to deselect another cell. In this way, each cell may be made up of a selection device and a crosspoint memory element in the same orientation. This may facilitate manufacturing and reduce costs in some embodiments.

Abstract: A process for the definition of integrated circuits on a wafer having at least one silicon semiconductor layer includes masking the wafer with a photoresist layer. The process includes a development step of the photoresist with definition of a lithographic pattern, a hardening step of the photoresist with a plasma of inert gas, and a dry etching step with a plasma of reactive gas for transferring the lithographic pattern on the wafer. The dry etching step includes at least an initial step, or breakthrough, with a plasma of a chlorinated gas and of an inert gas for removal of a silicon native oxide grown on the wafer.

Abstract: The method for block coding data, such as video data, via a compression operation includes applying to input-data blocks a discrete-cosine-transform (DCT) operation and a quantization operation to produce compressed-data blocks. The compressed-data blocks are subjected to a coding operation to obtain compressed output flows; and an inverse-quantization operation and an inverse-discrete-cosine-transform (IDCT) operation are applied on the compressed-data blocks to obtain reconstructed blocks. The method includes controlling generation of mismatch errors from the input-data blocks by detecting data blocks from the input-data blocks and compressed-data blocks that are liable to cause mismatch errors, and modifying the blocks that are liable to cause mismatch errors prior to the coding operation.

Abstract: A method for controlling the power factor of a power supply line is described, the method using a power factor control cell connected to the power supply line. Advantageously according to the invention, the power factor control is performed by adjusting the turn-on and turn-off time of a bipolar transistor comprised in the power factor control cell. A cell for controlling the power factor of a power supply line is also described, of the type comprising a first and a second input terminals, a first and a second output terminals, the first input terminal being connected to the first output terminal by means of the series of an inductor and a diode, connected to each other in correspondence with an internal circuit node and the second input terminal and the second output terminal being connected to each other.

Abstract: Color image signals, as derived, e.g., by interpolating the output from a color filter array are arranged in pixels, each pixel having associated detected color information for a first color as well as undetected filled-in color information for at least a second and a third color. The images are thus exposed to false color and zipper effect artifacts, and are subject to processing preferably including the steps of: checking the images for the presence of zipper effect artifacts, and i) if said checking reveals the presence of zipper effect artifacts, applying a zipper effect removal process to said image signals; ii) if said checking fails to reveal the presence of zipper effect artifacts, applying a false color removal process to said image signals. False color and zipper effect artifacts are thus preferably both reduced by adaptively using the zipper effect removal process and the false color removal process.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory matrix having a plurality of memory cells arranged according to a plurality of rows and a plurality of columns and a plurality of bit lines, each bit line being associated with at least one respective column of said plurality. The semiconductor memory device further includes a bit line selection structure for selecting at least one among said bit lines and a voltage clamping circuit structure adapted to cause the clamping at a prescribed voltage of unselected bit lines adjacent and capacitively coupled to a selected bit line during a read operation.

Abstract: Micro-electro-mechanical structure formed by a substrate of semiconductor material and a suspended mass extending above the substrate and separated therefrom by an air gap. An insulating region of a first electrically insulating material extends through the suspended mass and divides it into at least one first electrically insulated suspended region and one second electrically insulated suspended region. A plug element of a second electrically insulating material different from the first electrically insulating material is formed underneath the insulating region and constitutes a barrier between the insulating region and the air gap for preventing removal of the insulating region during fabrication, when an etching agent is used for removing a sacrificial layer and forming the air gap.

Abstract: An apparatus for the conversion of a digital input signal into an analog output signal, the apparatus including a first circuit receiving the digital input signal that is representative of the analog output signal and suitable for producing a first signal on an output line, and a second circuit for supplying a second signal on the output line, in response to a further digital signal. The further digital signal is a function of external variables, and the union of the first and second signal on the output line forms the analog output signal.