Abstract: The capacitive coupling between two adjacent bitlines of a NAND memory device may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them. The even (odd) bitlines that include cells not to be programmed are biased with a first voltage for inhibiting them from being programmed while the even (odd) bitlines that include cells to be programmed are grounded. The adjacent odd (even) bitlines are biased at the supply voltage or at an auxiliary voltage for boosting the bias voltage of the even (odd) bitlines above the supply voltage. The bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines.

Abstract: Transmission of multicast packets over a local area network is controlled by: identifying the condition where only a single receiver exists within the local area network for a given multicast group of packets, and allowing, upon occurrence of that condition, Automatic Repeat Request of the packets multicast towards said single receiver. A preferred field of application is wireless local area networks for use in a home environment.

Abstract: An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page. Each cell further includes an additional address loading flip-flop for loading the column address bit value input during ALE cycles for addressing the start memory location on the selected page during the ALE cycles. A logic circuit updates the address counting flip flop to the address bit value during a read confirm cycle in a read sequence, and during a first data input cycle in a program sequence.

Abstract: The method prevents oxidation or contamination phenomena of conductive interconnection structures in semiconductor devices and includes providing a layer of semiconductor or oxide base, a conductive layer or stack on the base layer, and an antireflection coating (ARC) layer on the conductive layer or stack. The method provides a thin dielectric covering layer on the antireflection coating layer to fill or cover the microfissures existing in the antireflection coating layer.

Abstract: An asynchronous set-reset circuit device for testing activity performed by an Automatic Test Patterns Generation tool may include a pair of logic gates having at least two inputs each, and a logic gate structure coupled upstream from the pair of logic gates. The logic gate structure may be for driving one respective input of the pair of logic gates and may have inputs receiving a pair of test command signals. The asynchronous set-reset circuit device may also include a plurality of feedback connections between outputs of the pair of logic gates and respective inputs of the logic gate structure.

Abstract: A monitoring device for an electric motor has in input a signal representing zero crossings of the back-electromotive force of the motor and comprises a monitor that detects the signal in first periods of time arranged around instants of time in which the zero crossings are expected. The device comprises a setting circuit that sets second periods of time that are less than the first periods of time and each second period of time is centered on the instant of time in which the zero crossing is expected. The monitor comprises a detector that tests whether each actual zero crossing occurs inside the second period of time and a controller that modifies by a quantity the subsequent period of electric revolution time between two consecutive expected instants of zero crossing if said actual zero crossing occurs outside the second period of time.

Abstract: A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

Abstract: A process for manufacturing an organic mask for the microelectronics industry, including forming an organic layer on a substrate; forming an inorganic mask on the organic layer; and etching selectively the organic layer through the inorganic mask. Furthermore, forming the inorganic mask includes forming at least a first auxiliary layer of a first inorganic material on the organic layer; forming a mask layer of a second inorganic material different from the first inorganic material on the first auxiliary layer; and shaping the mask layer using a dual-exposure lithographic process.

Abstract: A power converter having a noise component and a modulator configured to vary a frequency of the noise component of the power converter on the basis of a digital signal to be transmitted.

Abstract: A sensing circuit is provided. The sensing circuit is adapted to determine when a cell current flowing trough a selected memory cell exceeds a reference current during an evaluation phase of a sensing operation. The sensing circuit is adapted to be coupled to at least one selected memory cell through a respective bit line. The sensing circuit includes: an access circuit node adapted to be coupled to the bit line; precharging circuitry adapted to be activated in a precharge phase of the sensing operation preceding the evaluation phase, so as to bring a voltage of said access circuit node to a reference voltage; a reference circuit node coupled to the access circuit node and arranged to receive the reference current.

Abstract: A reading circuit for reading semiconductor memory cells, adapted to be coupled to at least one memory cell and to at least one reference cell through a respective bit line, the reading circuit including: a pre-charge circuit for pre-charging the bit lines to a predefined voltage during a pre-charge phase of a reading operation on the memory cell; a biasing circuit for applying a bias to a respective control terminal of the memory cell and of the reference cell in response to an enabling signal; and for each bit line, an evaluation circuit for evaluating an electric quantity developing on the bit line as a consequence of the bias during an evaluation phase of the reading operation on the memory cell, an information content of the memory cell being determined on the basis of the electric quantity that develops on the bit lines. The enabling signal is provided by the pre-charge circuit in response to an indication that the bit lines have reached the predefined voltage.

Abstract: An electroscope system excites a certain area of a surface of a sample to emit electrons with a characteristic distribution of kinetic energies. The analyzed area of the sample is excited by an electron beam produced by a field emission source. A monochromator energy filter for the electron beam is down-stream of the field emission source. The field emission electron source is preferably a Schottky source, and a monochromator energy filter reduces energy dispersion of the electrons of the electron beam to less than 0.2 eV. Microareas of linear dimensions on the order of ten nanometers may be analyzed while observing them. Information on the chemical state of the detected elements present at the surface of the examined microarea of the sample is gathered.

Abstract: A free-fall detector device includes an inertial sensor, a detection circuit associated to the inertial sensor, and a signal source for supplying a read signal to the inertial sensor. The device moreover includes: a storage element, selectively connectable to the detection circuit for storing a feedback signal generated by the detection circuit in response to the read signal supplied to the inertial sensor; and a feedback circuit coupled to the storage element for supplying the feedback signal to the inertial sensor so that the detection circuit generates at least one detection signal in response to the feedback signal supplied to the inertial sensor.

Abstract: A non-volatile memory device integrated on a semiconductor substrate of a first type of conductivity comprising a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of equidistantly spaced active areas with the non-volatile memory cells integrated therein, each non-volatile memory cell having a source region, a drain region and a floating gate electrode coupled to a control gate electrode, a group of the memory cells sharing a common source line of a second type of conductivity, an implanted region of said second type of conductivity inside at least one of the plurality of active areas in electric contact with the common source line, and at least one source contact aligned and in electric contact with the implanted region.

Abstract: A hosting structure of nanometric components is described comprising a substrate, a first multi-spacer level comprising a first plurality of spacers including first conductive spacers parallel to each other, and at least a second multi-spacer level realized above said first multi-spacer level and comprising a second plurality of spacers arranged transversally to said first plurality of spacers and including at least a lower discontinuous insulating layer and an upper layer, including in turn second conductive spacers. In particular, each pair of spacers of the second multi-spacer level defines with a spacer of the first multi-spacer level a plurality of nanometric hosting seats having at least a first and a second conduction terminal realized by portions of the first conductive spacers and of the second conductive spacers faced in the hosting seats. A method for manufacturing such a structure is also described.

Abstract: A reduced hardware control circuit device includes a current loop for broad band Hard Disk Drive applications. The current loop detects the value of the current flowing on the coils of a voice coil electric motor incorporated in the Hard Disk Drive. A sensing resistance is connected in series with the motor and at least a driving driver for a relative motor coil. Advantageously the current loop is a transconductance loop with a first transconductance amplifier associated with the sensing resistance. A second transconductance amplifier is provided for fixing the current value to be applied to the motor. The circuit device advantageously is deprived of a local compensation in correspondence with the first transconductance amplifier.

Abstract: Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times. Two separate bubblers may be utilized to feed the two organometallic compounds in gaseous form to the deposition chamber so that the relative proportions of the precursors can be readily controlled.

Abstract: A multistage circuit for regulating the charge voltage or the discharge current of a capacitance of an integrated device at a certain charge-pump generated boosted voltage is implemented without integrating high voltage transistor structures having a type of conductivity corresponding to the same sign of the boosted voltage (high-side transistors). The multistage circuit current includes at least a first stage, and an output stage in cascade to the first stage and coupled to the capacitance. The first stage is supplied at an unboosted power supply voltage of the integrated device, and the output stage is supplied at an unregulated charge-pump generated boosted voltage. The first stage includes a transistor having a type of conductivity corresponding to an opposite sign of the boosted voltage and of the power supply voltage. The drain of the output stage transistor is coupled to the boosted voltage either through a resistive pull-up or a voltage limiter.

Abstract: A method performs iterative decoding of information coded by an error correction code. The method includes: defining a transcendent first function representing a quantity to be evaluated for the decoding method; defining a quantized second function approximating the first function; computing first values of the second function obtained based on first arguments; the first values being not null and the first arguments being variable in a limited range having a maximum limit; computing second values of the second function obtained on the basis of second arguments, the second values being null; and generating a look-up table representing the first function and containing the first and second values associated to indexes correlated to said first arguments and to an expected maximum limit.

Abstract: An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type and a MOSFET of planar type, contiguous to one another. The active area accommodates a collector region; a bipolar base region contiguous to the collector region; an emitter region within the bipolar base region; a source region, arranged at a distance from the bipolar base region; a drain region; a channel region arranged between the source region and the drain region; and a well region. The drain region and the bipolar base region are contiguous and form a common base structure shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device has a high input impedance and is capable of driving high currents, while only requiring a small integration area.