Abstract: A reading circuit for reading semiconductor memory cells, adapted to be coupled to at least one memory cell and to at least one reference cell through a respective bit line, the reading circuit including: a pre-charge circuit for pre-charging the bit lines to a predefined voltage during a pre-charge phase of a reading operation on the memory cell; a biasing circuit for applying a bias to a respective control terminal of the memory cell and of the reference cell in response to an enabling signal; and for each bit line, an evaluation circuit for evaluating an electric quantity developing on the bit line as a consequence of the bias during an evaluation phase of the reading operation on the memory cell, an information content of the memory cell being determined on the basis of the electric quantity that develops on the bit lines. The enabling signal is provided by the pre-charge circuit in response to an indication that the bit lines have reached the predefined voltage.

Abstract: A method is provided for controlling a converter of the multiphase interleaving type. According to the method, there is detected when a change of the load applied to an output terminal of the converter occurs by detecting the derivative of a voltage signal of the output terminal. All the phases of the converter are simultaneously driven by zeroing a driving interleaving phase shift on the basis of the detected load transient, and the driving interleaving phase shift is recovered to restart a normal operation of the converter. A controller for carrying out such a method is also provided.

Abstract: A method is provided for controlling a converter of the multiphase interleaving type. According to the method, there is detected when a change of the load applied to an output terminal of the converter occurs. All the phases of the converter are simultaneously turned off, and a driving interleaving phase shift is recovered so as to restart a normal operation of the converter. A controller for carrying out such a method is also provided.

Abstract: An electroscope system excites a certain area of a surface of a sample to emit electrons with a characteristic distribution of kinetic energies. The analyzed area of the sample is excited by an electron beam produced by a field emission source. A monochromator energy filter for the electron beam is down-stream of the field emission source. The field emission electron source is preferably a Schottky source, and a monochromator energy filter reduces energy dispersion of the electrons of the electron beam to less than 0.2 eV. Microareas of linear dimensions on the order of ten nanometers may be analyzed while observing them. Information on the chemical state of the detected elements present at the surface of the examined microarea of the sample is gathered.

Abstract: A device of a plug-and-play type, which can be integrated in a home network having at least one audio-video Media-Server device or else at least one audio-video Media-Renderer device. The device can be activated for selectively configuring parameters and devices for setting up audio-video calls for connection between the home network and a packet network, such as the Internet. Preferentially, the device is based upon UPnP (Universal Plug-and-Play) technology and uses either a signaling protocol on IP packet network, such as the Session Initiation Protocol (SIP) and ITU-T H.323, or else mobile communications systems, such as the Universal Mobile Telecommunications System (UMTS). The device is able to redirect audio-video streams in the context of a plurality of devices capable of reproducing them and/or to selectively acquire said audio-video streams from a plurality of devices capable of supplying them.

Abstract: A free-fall detector device includes an inertial sensor, a detection circuit associated to the inertial sensor, and a signal source for supplying a read signal to the inertial sensor. The device moreover includes: a storage element, selectively connectable to the detection circuit for storing a feedback signal generated by the detection circuit in response to the read signal supplied to the inertial sensor; and a feedback circuit coupled to the storage element for supplying the feedback signal to the inertial sensor so that the detection circuit generates at least one detection signal in response to the feedback signal supplied to the inertial sensor.

Abstract: A non-volatile memory device integrated on a semiconductor substrate of a first type of conductivity comprising a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of equidistantly spaced active areas with the non-volatile memory cells integrated therein, each non-volatile memory cell having a source region, a drain region and a floating gate electrode coupled to a control gate electrode, a group of the memory cells sharing a common source line of a second type of conductivity, an implanted region of said second type of conductivity inside at least one of the plurality of active areas in electric contact with the common source line, and at least one source contact aligned and in electric contact with the implanted region.

Abstract: A non-volatile memory device integrated on semiconductor substrate and having a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of active areas formed on the semiconductor substrate equidistant from each other, and having at least a first and a second group of active areas; the non-volatile memory cells integrated in the first group of active areas, each non-volatile memory cell having a source region, a drain region, and a floating gate electrode coupled to a control gate electrode, at least one group of the memory cells sharing a common source region integrated on the semiconductor substrate; and a contact region integrated in the second group of active areas and provided with at least one common source contact of the common source region.

Abstract: A hosting structure of nanometric components is described comprising a substrate, a first multi-spacer level comprising a first plurality of spacers including first conductive spacers parallel to each other, and at least a second multi-spacer level realized above said first multi-spacer level and comprising a second plurality of spacers arranged transversally to said first plurality of spacers and including at least a lower discontinuous insulating layer and an upper layer, including in turn second conductive spacers. In particular, each pair of spacers of the second multi-spacer level defines with a spacer of the first multi-spacer level a plurality of nanometric hosting seats having at least a first and a second conduction terminal realized by portions of the first conductive spacers and of the second conductive spacers faced in the hosting seats. A method for manufacturing such a structure is also described.

Abstract: A reduced hardware control circuit device includes a current loop for broad band Hard Disk Drive applications. The current loop detects the value of the current flowing on the coils of a voice coil electric motor incorporated in the Hard Disk Drive. A sensing resistance is connected in series with the motor and at least a driving driver for a relative motor coil. Advantageously the current loop is a transconductance loop with a first transconductance amplifier associated with the sensing resistance. A second transconductance amplifier is provided for fixing the current value to be applied to the motor. The circuit device advantageously is deprived of a local compensation in correspondence with the first transconductance amplifier.

Abstract: Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times. Two separate bubblers may be utilized to feed the two organometallic compounds in gaseous form to the deposition chamber so that the relative proportions of the precursors can be readily controlled.

Abstract: A multistage circuit for regulating the charge voltage or the discharge current of a capacitance of an integrated device at a certain charge-pump generated boosted voltage is implemented without integrating high voltage transistor structures having a type of conductivity corresponding to the same sign of the boosted voltage (high-side transistors). The multistage circuit current includes at least a first stage, and an output stage in cascade to the first stage and coupled to the capacitance. The first stage is supplied at an unboosted power supply voltage of the integrated device, and the output stage is supplied at an unregulated charge-pump generated boosted voltage. The first stage includes a transistor having a type of conductivity corresponding to an opposite sign of the boosted voltage and of the power supply voltage. The drain of the output stage transistor is coupled to the boosted voltage either through a resistive pull-up or a voltage limiter.

Abstract: A detection circuit is provided with a differential capacitive sensor and with an interface circuit having a first sense input and a second sense input, electrically connected to the differential capacitive sensor. Provided in the interface circuit are: a sense amplifier connected at input to the first sense input and to the second sense input and supplying an output signal related to a capacitive unbalancing of the differential capacitive sensor; and a common-mode control circuit, connected to the first sense input and to the second sense input and configured to control a common-mode electrical quantity present on the first sense input and on the second sense input. The common-mode control circuit is of a totally passive type and is provided with a capacitive circuit, which is substantially identical to an equivalent electrical circuit of the differential capacitive sensor and is driven with a driving signal in phase opposition with respect to a read signal supplied to the differential capacitive sensor.

Abstract: A method performs iterative decoding of information coded by an error correction code. The method includes: defining a transcendent first function representing a quantity to be evaluated for the decoding method; defining a quantized second function approximating the first function; computing first values of the second function obtained based on first arguments; the first values being not null and the first arguments being variable in a limited range having a maximum limit; computing second values of the second function obtained on the basis of second arguments, the second values being null; and generating a look-up table representing the first function and containing the first and second values associated to indexes correlated to said first arguments and to an expected maximum limit.

Abstract: An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type and a MOSFET of planar type, contiguous to one another. The active area accommodates a collector region; a bipolar base region contiguous to the collector region; an emitter region within the bipolar base region; a source region, arranged at a distance from the bipolar base region; a drain region; a channel region arranged between the source region and the drain region; and a well region. The drain region and the bipolar base region are contiguous and form a common base structure shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device has a high input impedance and is capable of driving high currents, while only requiring a small integration area.

Abstract: A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.

Abstract: A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. Each block including at least one failed cell in the first subset is located during a test on wafer of the non-volatile memory device. Each block is marked as bad, and a bad block address table of respective codes is stored in a non-volatile memory buffer. At power-on, the bad block address table is copied from the non-volatile memory buffer to the random access memory. A block of memory cells of the first subset is verified as bad by looking up the bad block address table, and if a block is bad, then remapping access to a corresponding block of redundancy cells.

Abstract: A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region.

Abstract: A control device for a switching converter has an input terminal and an output terminal; the converter includes a half-bridge of a first and a second transistor coupled between the input terminal and a reference voltage. The control device detects a signal on the output terminal of the converter, integrates the detected signal and imposes a predefined minimum frequency of the detected signal. The control device regulates the average value of the detected signal by comparison with a reference signal and drives the first and second transistors in during the regulation. The control device turns off an integrator when the predefined minimum frequency is imposed.

Abstract: A system renders a primitive of an image to be displayed, for instance in a mobile 3D graphic pipeline, the primitive including a set of pixels. The system locates the pixels in the area of the primitive, generates, for each pixel located in the area, a set of associated sub-pixels, borrows a set of sub-pixels from neighboring pixels, subjects the set of associated sub-pixels and the borrowed set of pixels to adaptive filtering to create an adaptively filtered set of sub-pixels, and further filters the adaptively filtered set of sub-pixels to compute a final pixel for display. Preferably, the set of associated sub-pixels fulfils at least one of the following: the set includes two associated sub-pixels and the set includes associated sub-pixels placed on triangle edges.