Abstract: A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.

Abstract: A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. Each block including at least one failed cell in the first subset is located during a test on wafer of the non-volatile memory device. Each block is marked as bad, and a bad block address table of respective codes is stored in a non-volatile memory buffer. At power-on, the bad block address table is copied from the non-volatile memory buffer to the random access memory. A block of memory cells of the first subset is verified as bad by looking up the bad block address table, and if a block is bad, then remapping access to a corresponding block of redundancy cells.

Abstract: A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region.

Abstract: A control device for a switching converter has an input terminal and an output terminal; the converter includes a half-bridge of a first and a second transistor coupled between the input terminal and a reference voltage. The control device detects a signal on the output terminal of the converter, integrates the detected signal and imposes a predefined minimum frequency of the detected signal. The control device regulates the average value of the detected signal by comparison with a reference signal and drives the first and second transistors in during the regulation. The control device turns off an integrator when the predefined minimum frequency is imposed.

Abstract: A system renders a primitive of an image to be displayed, for instance in a mobile 3D graphic pipeline, the primitive including a set of pixels. The system locates the pixels in the area of the primitive, generates, for each pixel located in the area, a set of associated sub-pixels, borrows a set of sub-pixels from neighboring pixels, subjects the set of associated sub-pixels and the borrowed set of pixels to adaptive filtering to create an adaptively filtered set of sub-pixels, and further filters the adaptively filtered set of sub-pixels to compute a final pixel for display. Preferably, the set of associated sub-pixels fulfils at least one of the following: the set includes two associated sub-pixels and the set includes associated sub-pixels placed on triangle edges.

Abstract: A method for controlling a PWM power stage is based upon dampening current peaks generated by switching of the PWM power stage. The PWM power stage includes at least two MOS transistors of opposite conductivity coupled between an output node of the PWM power stage and respective positive and negative supply lines, and respective free-wheeling diodes. The method includes forming the at least two MOS transistors such that their reverse conduction threshold voltage is smaller than a sum between their forward conduction threshold voltage and a forward voltage on the respective free-wheeling diode at which a pre-established current flows therethrough. The at least two MOS transistors are in a high impedance state by biasing respective control nodes at a turn-off voltage such that their gate-source voltage is between the forward conduction threshold voltage and a null voltage.

Abstract: A stacked die semiconductor package includes: a substrate, having a first surface and an opposite surface thereto; a plurality of dice, structured for being stacked one on top of the other on the first surface of the substrate, including at least a first die which is mounted closest to the first surface, a second die mounted thereupon and having a larger footprint area than the first die, and a top die having a smaller footprint area than the underlying die thereof, and each having a plurality of contact pads and a plurality of wires for electrically connecting the dice to the first surface of the substrate; at least one interposer between the plurality of dice; advantageously, said top die is electrically directly connected to one of the underlying dice. A method for the assembly of a stacked die semiconductor package is provided.

Abstract: A phase change memory cell includes a phase change region of a phase change material, a heating element of a resistive material, arranged in contact with the phase change region and a memory element formed in said phase change region at a contact area with the heating element. The contact area is in the form of a frame that has a width of sublithographic extent and, preferably, a sublithographic maximum external dimension. The heating element includes a hollow elongated portion which is arranged in contact with the phase change region.

Abstract: An interface device having a first and second data terminal configured for the communication of data in duplex mode, with one of the first and second data terminals always assigned to each direction of the communication, the first and second data terminals configurable during operation such that, in a first mode of operation, the first data terminal is configured to send but not to receive data and the second data terminal is configured to receive but not send data, while in a second mode of operation the first data terminal is configured to receive but not to send data and the second data terminal is configured to send but not to receive data.

Abstract: A four-level FLASH memory device includes an array of singularly addressable preliminarily erased memory cells, with each memory cell capable of storing a two-bit datum. When the threshold voltage of a memory cell is verified to have reached the desired distribution, the cell is read using a test read voltage smaller than or equal to the program voltage. In this situation the voltage VS on the source node is negligible, and the programmed state of the cell may be correctly verified.

Abstract: A method realizes an electric connection between a nanometric circuit and standard electronic components. The method includes: providing, above a semiconductor substrate, a seed having a notched wall substantially perpendicular to the substrate, the wall having n recesses spaced apart from one another; and realizing n conductive nanowires alternated with insulating nanowires. Each realization of a conductive nanowire fills a corresponding recess by a respective elbow-like portion of the conductive nanowire, and partially fills the other recesses by respective notched profile portions, thereby forming the nanometric circuit.

Abstract: An architecture for implementing an integrated capacity advantageously includes a capacitive block inserted between a first and a second voltage reference. The block is formed from elementary capacitive modules. An enable block is inserted between the first voltage reference and the capacitive block and includes switches connected to the elementary capacitive modules and driven on their control terminals by control signals. Each switch of the enable block is inserted between the first voltage reference and a first end of a corresponding elementary capacitive module. A verify and enable circuit is connected to the first voltage reference, as well as at the input of the first end of the elementary capacitive modules and at the output of the control terminals of the switches of the enable block.

Abstract: A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.

Abstract: A non-volatile memory device of flash type includes first memory cells for storing data, second memory cells for storing protection information of the first memory cells, and a circuit for updating the protection information that includes a circuit for writing a plurality of versions of the protection information in the second memory cells, and a circuit for identifying a current version of the protection information.

Abstract: An arrangement is for measuring characteristic parameters of intermodulation distortion of a device under test. The arrangement may include a generator of at least two tones at different test frequencies, and an attenuation path feeding the device with a replica of the two tones attenuated of a factor equal to the gain of the device. The arrangement may also include a circuit for generating a difference signal between the signal output by the device and the two tones, and a circuit input with the difference signal and measuring the characteristic parameters as a function thereof.

Abstract: A memory includes a phase change memory element having a memory layer of a calcogenide material and a glue layer of an alloy of the form TiaXbNc where X is selected in the group comprising silicon, aluminum, carbon, or boron, and c may be 0. The nitrogen and silicon are adapted to reduce the diffusion of titanium toward the chalcogenide layer.

Abstract: A single-ended or differential single-stage, or multi-stage sigma-delta analog-to-digital converter includes at least one switched-capacitor integrator comprising a switched-capacitor network receiving as input a signal to be sampled, and an amplifier coupled in cascade to the switched-capacitor network. A circuit is coupled to the amplifier for feeding an analog dither signal to a virtual ground of the amplifier.

Abstract: An array of non-volatile memory cells includes a row with N cells and M cells. In a partial-storage step, a datum is stored in a first portion of the N cells of the row. A second portion of the N cells of the row are in an “erase” state. A first error correction code associated with the datum is stored in the M cells along with a first enable bit or guard-cell which is indicative of whether the first error correction code is active. The number of M cells, adjacent to the N cells of the row, is defined on the basis of the number N of cells. In the event the datum stored in the first portion of the N cells of the row is subsequently updated or manipulated, a second error correction code associated with the updated or manipulated datum is determined and stored in the second portion of the N cells of the row along with a second enable bit or guard-cell which is indicative of whether the second error correction code is active.

Abstract: The errors that may occur in transmitted numerical data on a channel affected by burst errors, are corrected via the operations of: ordering the numerical data in blocks each comprising a definite number of data packets; generating for each block a respective set of error-correction packets comprising a respective number of correction packets, the respective number identifying a level of redundancy for correcting the errors; and modifying dynamically the level of redundancy according to the characteristics of the bursts and of the correct-reception intervals between two bursts. Preferential application is on local networks, such as W-LANs for use in the domestic environments.

Abstract: A non-volatile memory device includes an array of memory cells organized into a plurality of array sectors, with each array sector being singularly addressable through an array wordline. An array of reference cells is addressable through a reference wordline. A respective voltage ramp generator is provided for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and is provided for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein. A respective row decoding circuit is coupled between each respective volage ramp generator and corresponding reference wordline or array wordline. A current generator generates a current to be injected on a circuit node in a selected array sector and on a circuit node of the array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp.