Abstract: A method of testing a photonic device includes providing a plurality of optical test signals at respective inputs of a first plurality of inputs of an optical input circuit located on a substrate, combining the plurality of optical test signals into a combined optical test signal at an output of the optical input circuit, transmitting the combined optical test signal through the output to an input waveguide of an optical device under test, the optical device under test being located on the substrate, and measuring a response of the optical device under test to the combined optical test signal. Each of the plurality of optical test signals comprises a respective dominant wavelength of a plurality of dominant wavelengths.

Abstract: In an embodiment a control device includes a first input configured to receive a measurement signal representative of an output voltage of a switching circuit of a voltage regulator, a state determination block coupled to the first input and configured to generate a signal of actual operating condition of the voltage regulator and a driving signals generation module configured to generate at least one switching command signal for the switching circuit from an error signal representative of a difference between the output voltage and a nominal voltage, wherein the driving signals generation module includes an error-compensation circuit having a transfer function and configured to generate a control signal from the error signal and the actual operating condition signal, the control signal being a function of the actual operating condition.

Abstract: In accordance with an embodiment, a system includes a phase-locked loop (PLL) configured to provide a first local oscillator (LO) signal and a voltage-controlled oscillator (VCO) signal; a first quadrature demodulator configured to downconvert global navigation satellite system signals to produce a first intermediate frequency (IF) signal; a first signal processing chain configured to pass the first IF signal; a second signal processing chain comprising a first frequency divider configured to produce a second LO signal based on the first LO signal, and a second quadrature demodulator configured to convert the first IF signal to a second IF signal using the second LO signal; and a third signal processing chain comprising a second frequency divider configured to produce a third LO signal based on the VCO signal, and a third quadrature demodulator configured to convert the first IF signal to a third IF signal using the third LO signal.

Abstract: A system including an asynchronous finite state machine that transitions from a first state to a second state in response to receiving a virtual-clock event signal. The system further includes a trigger circuit that asserts a trigger signal when a first-state asynchronous event signal is asserted while the asynchronous finite state machine is in the first state. The system further including a virtual clock-pulse circuit configured to generate the virtual-clock event signal after receiving the trigger signal.

Abstract: A control circuit and method, wherein an error signal is generated representative of a difference between an output voltage of a switching circuit and a nominal signal; a single control signal is generated, representative of an average error of the error signal; the single control signal is compared with a first periodic reference signal and a second periodic reference signal; a first pulse width modulated signal is generated by a Buck modulator; and a second pulse width modulated signal is generated by a Boost modulator. The maximum value of the first periodic reference signal and the minimum value of the second periodic reference signal are higher and lower, respectively, than the single control signal in a transient control mode between a Buck control mode and a Boost control mode.

Abstract: An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region.

Abstract: A method for manufacturing an ohmic contact for a HEMT device, comprising the steps of: forming a photoresist layer, on a semiconductor body comprising a heterostructure; forming, in the photoresist layer, an opening, through which a surface region of the semiconductor body is exposed at said heterostructure; etching the surface region of the semiconductor body using the photoresist layer as etching mask to form a trench in the heterostructure; depositing one or more metal layers in said trench and on the photoresist layer; and carrying out a process of lift-off of the photoresist layer.

Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.

Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

Abstract: A control circuit operates to control a switching stage of an electronic converter. The control circuit includes: first terminals providing drive signals to electronic switches of the switching stage; a second terminal receiving from a feedback circuit a first feedback signal proportional to a converter output voltage; and a third terminal configured to receive from a current sensor a second feedback signal proportional to an inductor current. A driver circuit provides the drive signals as a function of a PWM signal generated by a generator circuit as a function of the first and second feedback signals, a reference voltage and a slope compensation signal. A mode selection signal is generated as a function of a comparison between the input voltage and the output voltage. A feed-forward compensation circuit is configured to source and/or sink a compensation current as a function of a variation in the mode selection signal.

Abstract: A method of manufacturing semiconductor devices, such as QFN/BGA flip-chip type packages, arranging on a leadframe one or more semiconductor chips or dice having a first side facing towards the leadframe and electrically coupled therewith and a second side facing away from the leadframe. The method also includes molding an encapsulation on the semiconductor chip(s) arranged on the leadframe, where the encapsulation has an outer surface opposite the leadframe and comprises laser direct structuring (LDS) material. Laser direct structuring processing is applied to the LDS material of the encapsulation to provide metal vias between the outer surface of the encapsulation and the second side of the semiconductor chip(s) and as well as a metal pad at the outer surface of the encapsulation.

Abstract: A semiconductor device, such as a Quad-Flat No-lead (QFN) package, includes a semiconductor chip arranged on a die pad of a leadframe. The leadframe has an array of electrically-conductive leads around the die pad. The leads in the array have distal ends facing away from the die pad as well as recessed portions at an upper surface of the leads. Resilient material, such as low elasticity modulus material, is present at the upper surface of the leads and filling the recessed portions. An insulating encapsulation is molded onto the semiconductor chip. The resilient material is sandwiched between the insulating encapsulation and the distal ends of the leads. This resilient material facilitates flexibility of the leads, making them suited for reliable soldering to an insulated metal substrate.

Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

Abstract: A driving circuit for controlling a MEMS oscillator includes a digital conversion stage to acquire a differential sensing signal indicative of a displacement of a movable mass of the MEMS oscillator, and to convert the differential sensing signal of analog type into a digital differential signal of digital type. Processing circuitry is configured to generate a digital control signal of digital type as a function of the comparison between the digital differential signal and a differential reference signal indicative of a target amplitude of oscillation of the movable mass which causes the resonance of the MEMS oscillator. An analog conversion stage includes a ?? DAC and is configured to convert the digital control signal into a PDM control signal of analog type. A filtering stage of low-pass type, by filtering the PDM control signal, generates a control signal for controlling the amplitude of oscillation of the movable mass.

Abstract: A flash analog-to-digital converter (ADC) receives an input control signal and performs coarse tuning of a frequency of an output signal, produced between first and second nodes having an inductance coupled therebetween. The flash ADC quantizes an operating frequency range for the output signal produced between the first and second nodes as M·?f, where M is an integer from 0 to N?1, where N is a number of intervals into which a frequency range for the output signal is divided, and where ?f is a resulting frequency step produced by the quantizing. The value of M is generated based upon the input control signal and a word controlling switches of a plurality of switched capacitance circuits associated with the first and second nodes to close ones of those switches associated with the control word to coarsely tune the frequency of the output signal.

Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A switching circuit is connected between each bit line and a corresponding column output. The switching circuit is controlled to turn on to generate the analog signal dependent on the computational weight and for a time duration controlled by the coefficient data signal. A column combining circuit combines (by addition and/or subtraction) and integrates analog signals at the column outputs of the biasing circuits. The addition/subtraction is dependent on one or more a sign of the coefficient data and a sign of the computational weight and may further implement a binary weighting function.

Abstract: A MEMS actuator includes a mobile mass suspended over a substrate in a first direction and extending in a plane that defines a second direction and a third direction perpendicular thereto. Elastic elements arranged between the substrate and the mobile mass have a first compliance in a direction parallel to the first direction that is lower than a second compliance in a direction parallel to the second direction. Piezoelectric actuation structures have a portion fixed with respect to the substrate and a portion that deforms in the first direction in response to an actuation voltage. Movement-transformation structures coupled to the piezoelectric actuation structures include an elastic movement-conversion structure arranged between the piezoelectric actuation structures and the mobile mass. The elastic movement-conversion structure is compliant in a plane formed by the first and second directions and has first and second principal axes of inertia transverse to the first and second directions.

Abstract: A method for accessing memory cells in an array of memory cells storing respective data signals, wherein memory cells in the array of memory cells have a first, resp. second, node selectively couplable to respective bitline branches in a first, resp. second, set of bitline branches, wherein the first and the second set of bitline branches provide at least one bitline capacitance configured to store a bias level of charge in response to being charged.

Abstract: An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.

Abstract: A method for manufacturing a SiC-based electronic device, that includes implanting, at a front side of a solid body of SiC having a conductivity of N type, dopant species of P type, thus forming an implanted region that extends in depth in the solid body starting from the front side and has a top surface co-planar with said front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region at temperatures comprised between 1500° C. and 2600° C. so as to form an ohmic contact region including one or more carbon-rich layers, for example graphene and/or graphite layers, in the implanted region and, simultaneously, activation of the dopant species of P type.