Patents Assigned to STMicroelectronics S.r.l.
  • Patent number: 10930799
    Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: February 23, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Flavio Francesco Villa, Marco Morelli, Marco Marchesi, Simone Dario Mariani, Fabrizio Fausto Renzo Toia
  • Patent number: 10930581
    Abstract: Embodiments of the present disclosure are directed to flat no-lead packages with wettable sidewalls or flanks. In particular, wettable conductive layers are formed on the package over lateral portions of the leads and on portions of the package body, which may be encapsulation material. The wettable conductive layers may also be formed on bottom surfaces of the package body and the leads. The wettable conductive layers provide a wettable flank for solder to wick up when the package is mounted to a substrate, such as a PCB, using SMT. In particular, solder that is used to join the PCB and the package wicks up the side of the wettable conductive layers along a side surface of the package. In that regard, the solder is exposed and coupled to the side surface of the package at the wettable conductive layers, thereby allowing for a visual inspection of the solder joints. The wettable conductive layers are formed on the package after the package body has been formed.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: February 23, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Publication number: 20210050226
    Abstract: Semiconductor dice are arranged on a substrate such as a leadframe. Each semiconductor die is provided with electrically-conductive protrusions (such as electroplated pillars or bumps) protruding from the semiconductor die opposite the substrate. Laser direct structuring material is molded onto the substrate to cover the semiconductor dice arranged thereon, with the molding operation leaving a distal end of the electrically-conductive protrusion to be optically detectable at the surface of the laser direct structuring material. Laser beam processing the laser direct structuring material is then performed with laser beam energy applied at positions of the surface of the laser direct structuring material which are located by using the electrically-conductive protrusions optically detectable at the surface of the laser direct structuring material as a spatial reference.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 18, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Michele DERAI, Giovanni GRAZIOSI
  • Publication number: 20210050859
    Abstract: A multiple-input analog-to-digital converter device includes analog-to-digital converter circuits arranged between input nodes and output nodes. The analog-to-digital converter circuits operate over respective conversion times to provide simultaneous conversion of the analog input signals into respective conversion time signals. A time-to-digital converter circuit includes timer circuitry common to the plurality of analog-to-digital converter circuits. The timer circuitry cooperates with the analog-to-digital converter circuits to convert the conversion time signals into digital output signals at the output nodes.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 18, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giovanni SICURELLA, Manuela LA ROSA
  • Patent number: 10921122
    Abstract: A sensor includes an accelerometer, which, in operation, generates accelerometer data, and digital signal processing circuitry. The digital signal processing circuitry, in operation, generates, based on the generated accelerometer data, a value indicative of a cosine of an angle between an acceleration vector associated with current accelerometer data and a reference acceleration vector, compares the generated value indicative of the cosine of the angle between the vector associated with current accelerometer data and the reference acceleration vector with one or more thresholds and generates a tilt signal based on the comparison of the generated value indicative of the cosine of the angle between the vector associated with current accelerometer data and the reference acceleration vector with the one or more thresholds. The tilt signal may be used as an interrupt signal to an application processor.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: February 16, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Marco Leo, Paolo Rosingana, Marco Castellano
  • Patent number: 10921164
    Abstract: A MEMS sensor generates an output multiscale reading signal supplied to a full scale adjustment stage. The full scale adjustment stage includes a signal input configured to receive the reading signal, a saturation assessment block, and a full scale change block. The saturation assessment block is coupled to the signal input and configured to generate a scale increase request signal upon detection of a saturation condition. The full scale change block is coupled to the saturation assessment block and configured to generate a full scale change signal upon reception of the scale increase request signal.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 16, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Matteo Quartiroli
  • Patent number: 10922807
    Abstract: A device includes image generation circuitry and a convolutional neural network. The image generation circuitry, in operation, generates a binned representation of a wafer defect map (WDM). The convolutional-neural-network, in operation, generates and outputs an indication of a root cause of a defect associated with the WDM based on the binned representation of the WDM and a data-driven model associating WDMs with classes of a defined set of classes of wafer defects.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: February 16, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Lidia Moioli, Pasqualina Fragneto, Beatrice Rossi, Diego Carrera, Giacomo Boracchi, Mauro Fumagalli, Elena Tagliabue, Paolo Giugni, Annalisa Aurigemma
  • Patent number: 10924100
    Abstract: An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: February 16, 2021
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Alps) SAS
    Inventors: Giovanni Luca Torrisi, Domenico Porto, Christophe Roussel
  • Patent number: 10924194
    Abstract: A radio-frequency transceiver device includes a transmission circuit generating a transmission signal at a transmission pad connected to a transmission antenna by modulating a radio frequency signal as a function of a control signal. First and second reception circuits receive first and second signals at first and second reception pads connected to first and second reception antennas. The received first and second signals are demodulated via the radio frequency signal to generate first and second demodulated reception signals. A control circuit operates during a reception test phase to generate only the control signal in order to test, as a function of the first and second demodulated reception signals, whether the received first signal corresponds to the received second signal. A reception error signal indicating a reception error is generated when the test indicates that the received first and second reception signals do not correspond.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 16, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventor: Francesco Belfiore
  • Patent number: 10914647
    Abstract: A capacitive sensor for monitoring stresses acting in a construction structure and having a multi-layer structure provided with an upper conductive layer defining an upper outer surface of the sensor. A lower conductive layer defines a lower outer surface. At least a first structural layer of insulating material is in contact with the upper conductive layer and at least a second structural layer of insulating material is in contact with the lower conductive layer. At least a first plate layer of conductive material and at least a second plate layer, of conductive material, and at least one dielectric layer is interposed between the first plate layer and the second plate layer to define at least one detection capacitor inside the multi-layer structure of the sensor. The upper and lower conductive layers jointly defining an electromagnetic screen for screening the detection capacitor against electromagnetic interference originating from outside the capacitive sensor.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: February 9, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Francesco Pappalardo, Agatino Pennisi, Elio Guidetti, Angelo Doriani
  • Patent number: 10917087
    Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: February 9, 2021
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS, Inc., STMICROELECTRONICS (ALPS) SAS
    Inventors: Vanni Poletto, David F. Swanson, Giovanni Luca Torrisi, Laurent Chevalier
  • Patent number: 10914938
    Abstract: An oscillating structure includes first and second torsional elastic elements that define an axis of rotation and a moving element that is interposed between the first and second torsional elastic elements. The moving element, the first torsional elastic element and the second torsional elastic element lie in a first plane and are not in direct contact with one another. A coupling structure mechanically couples the moving element, the first torsional elastic element and the second torsional elastic element together. The moving element, the first torsional elastic element and the second torsional elastic element lie in a second plane different from the first plane. Oscillation of the moving element occurs as a result of a twisting of the first and second torsional elastic elements.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: February 9, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Carminati, Sonia Costantini, Marta Carminati
  • Patent number: 10916622
    Abstract: In various embodiments, the present disclosure provides capacitors and methods of forming capacitors. In one embodiment, a capacitor includes a substrate, a first electrode on the substrate, a second electrode, and a first dielectric layer. A portion of the first electrode is exposed in a contact region. The first dielectric layer includes a first dielectric region between the first electrode and the second electrode, and a second dielectric region between the first dielectric region and the contact region. The second dielectric region is contiguous to the first dielectric region, and a surface of the second dielectric region defines a surface path between the first electrode and the contact region. The second dielectric region has a plurality of grooves that increase a spatial extension of said surface path.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: February 9, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Davide Giuseppe Patti, Giuseppina Valvo, DelfoNunziato Sanfilippo
  • Patent number: 10917091
    Abstract: An oscillator is coupled to a first side of a galvanic barrier for supplying thereto an electric supply signal. The oscillator is configured to be alternatively turned on and off as a function of a PWM drive signal applied thereto. A receiver circuit coupled to the galvanic barrier receives therefrom a PWM power control signal. A signal reconstruction circuit coupled between the receiver circuit block and the oscillator provides to the oscillator a PWM drive signal reconstructed from the PWM power control signal. The signal reconstruction circuit includes a PLL circuit coupled to the receiver circuit block and configured to lock to the PWM control signal from the receiver circuit block. A PLL loop within the PLL circuit is sensitive to the PWM drive signal applied to the oscillator. The PLL loop is configured to be opened as a result of the power supply oscillator being turned off.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: February 9, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Parisi, Nunzio Greco, Nunzio Spina, Egidio Ragonese, Giuseppe Palmisano
  • Publication number: 20210035894
    Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.
    Type: Application
    Filed: July 28, 2020
    Publication date: February 4, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventor: Fulvio Vittorio FONTANA
  • Patent number: 10906801
    Abstract: An integrated device includes: a first die; a second die coupled in a stacked way on the first die along a vertical axis; a coupling region arranged between facing surfaces of the first die and of the second die, which face one another along the vertical axis and lie in a horizontal plane orthogonal to the vertical axis, for mechanical coupling of the first and second dies; electrical-contact elements carried by the facing surfaces of the first and second dies, aligned in pairs along the vertical axis; and conductive regions arranged between the pairs of electrical-contact elements carried by the facing surfaces of the first and second dies, for their electrical coupling. Supporting elements are arranged at the facing surface of at least one of the first and second dies and elastically support respective electrical-contact elements.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: February 2, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Enri Duqi, Lorenzo Baldo, Domenico Giusti
  • Patent number: 10910500
    Abstract: In an embodiment of the present invention, a load sensor package includes a housing having a cap, a column, a peripheral structure, and a base. The base includes a major surface configured to mount a stress sensor, while the cap includes a cap major surface configured to receive a load to be measured. The column is configured to transfer a predetermined fraction of the load to be measured to the base through the stress sensor. The peripheral structure is configured to transfer the remaining fraction of the load to be measured to the base.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: February 2, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mohammad Abbasi Gavarti, Daniele Caltabiano, Marco Omar Ghidoni
  • Patent number: 10910302
    Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: February 2, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca Stella, Agatino Minotti
  • Patent number: 10910510
    Abstract: The disclosure relates to an encapsulated flexible electronic device comprising a flexible electronic device, wherein the flexible electronic device is protected by a protective coating layer, a first cover sheet and a second cover sheet being made of patterned and developed dry photoresist films. The encapsulated flexible electronic device may be used to directly realize different type of electronic devices, such as smart sensor devices.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: February 2, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Corrado Accardi, Stella Loverso, Sebastiano Ravesi, Noemi Graziana Sparta
  • Patent number: 10910558
    Abstract: A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer made of a first alloy of germanium, antimony, and tellurium. In a programmed state, resulting from heating a portion of the stack to a sufficient temperature, portions of layers of germanium and of the first alloy form a second alloy made up of germanium, antimony, and tellurium, where the second alloy has a higher germanium concentration than the first alloy.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: February 2, 2021
    Assignees: STMicroelectronics S.r.l., Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Paolo Giuseppe Cappelletti, Gabriele Navarro