Abstract: A switching circuit for transmission channel for ultrasound applications is electrically coupled between a connection terminal and a low voltage output terminal. The switching circuit includes a receiving switch, a high voltage clamp circuit electrically coupled between the connection terminal and a central node, and a low voltage clamping switch electrically coupled between said central node and a reference voltage. The receiving switch is a low voltage switch and is electrically coupled between the central node and the low voltage output terminal. The clamping switch and the receiving switch are controlled in a complementary way with respect to each other. A transmission channel for ultrasound applications includes the switching circuit.
Type:
Grant
Filed:
May 31, 2013
Date of Patent:
September 27, 2016
Assignee:
STMicroelectronics S.r.l.
Inventors:
Davide Ugo Ghisu, Antonio Ricciardo, Sandro Rossi
Abstract: A method and apparatus for compensating current leakage is disclosed. In the method and apparatus, a differential amplifier receives a first input signal and a second input signal and outputs a first output signal and a second output signal. The first output signal is filtered to obtain a first filtered signal. The first filtered signal is compared to the first input signal and a first compensation signal is outputted having a first voltage that is a function of a difference between a voltage of the first filtered signal and a voltage of the first input signal. Current leakage in the first input signal is compensated for using the first compensation signal.
Abstract: A interface circuit for an acoustic transducer provided with a first detection structure and a second detection structure has: a first input and a second input; a first processing path and a second processing path coupled, respectively, to the first input and second input and supply a first processed signal and a second processed signal; and a recombination stage, which supplies a mixed signal by combining the first processed signal and the second processed signal with a respective weight that is a function of a first level value of the first processed signal. The first and second inputs receive a respective detection signal associated, respectively, to the first detection structure and to the second detection structure of the acoustic transducer; and an output stage the first processed signal, the second processed signal or the mixed signal, on the basis of a second level value of the first processed signal.
Abstract: One or more first signals and one or more second signals, wherein the second signal(s) are slowly varying or low frequency signals in comparison with the first signals and are converted from analog to digital by sampling the first signals and the second signals to produce samples thereof for analog-to-digital conversion, subjecting the samples of the first signals to conversion to digital at a certain conversion rate, subjecting the samples of the second signal to conversion to digital by segments so that these segments are subjected to conversion to digital along with the samples of the first signals at the respective conversion rate, and reconstructing digital converted samples of the second signal from the segments subjected to conversion to digital.
Type:
Grant
Filed:
September 23, 2015
Date of Patent:
September 27, 2016
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Matteo Quartiroli, Salvatore Poli, Roberto Faravelli, Giovanni Carlo Tripoli
Abstract: A failure diagnosis circuit includes a multiplexer and a controller. The multiplexer receives address signals, and selectively outputs one of the address signals to an addressable module in response to a selecting signal. The controller generates a first one of address signals and the selecting signal. A built-in self-test circuit generates the second address signal. The addressable module includes addressable components responsive to the address signal. The controller processes the output of the addressable module responsive to the address signal to make a failure diagnosis. The built-in self-test circuit performs signature analysis on the read out output of the addressable module.
Abstract: An energy-harvesting system includes a transducer to convert environmental energy into a harvesting electrical signal. A storage element stores electrical energy derived from conversion of the harvested environmental energy. A harvesting interface supplies an electrical charging signal to the storage element. The harvesting interface is selectively connected to the storage element in response to a control signal. The control signal causes the connection when the harvesting electrical signal exceeds a threshold. Conversely, the control signal causes the disconnection when the harvesting electrical signal is less than the threshold.
Abstract: A microelectromechanical device includes: a body; a movable mass, elastically coupled to the body and oscillatable with respect to the body according to a degree of freedom; a frequency detector, configured to detect a current oscillation frequency of the movable mass; and a forcing stage, capacitively coupled to the movable mass and configured to provide energy to the movable mass through forcing signals having a forcing frequency equal to the current oscillation frequency detected by the frequency detector, at least in a first transient operating condition.
Type:
Grant
Filed:
March 13, 2013
Date of Patent:
September 20, 2016
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Marco Garbarino, Andrea Donadel, Davide Magnoni, Carlo Valzasina
Abstract: An IC may include a substrate and a layer, and an array of GMAPDs in the layer. The layer may have trenches extending between adjacent GMAPDs. The IC may include an optically reflective material within the trenches. The optically reflective material may also be electrically conductive. For example, the optically reflective material may comprise a metal. Also, the trenches may be arranged in a honeycomb pattern.
Type:
Grant
Filed:
May 28, 2015
Date of Patent:
September 20, 2016
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Lorenzo Motta, Claudio Alfonso Giacomo Savoia
Abstract: A DC-DC converter independently supplies electrical loads. For each load, an output load signal is compared to a reference to generate a result indicating a need to supply the respective electrical load. A first detection is made as to whether a first electrical load needs to be supplied and a second detection is made as to whether any remaining electrical loads need to be supplied. The first electrical load is supplied if the first detection is positive and the second detection is negative.
Type:
Grant
Filed:
February 14, 2014
Date of Patent:
September 20, 2016
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Alessandro Gasparini, Eugenio Miluzzi, Alberto Cattani, Stefano Ramorini
Abstract: An electronic semiconductor device including a semiconductor body having a first structural region and a second structural region, which extends on the first structural region and houses a drain region; a body region, which extends into the second structural region; a source region, which extends into the body region; and a gate electrode, which extends over the semiconductor body for generating a conductive channel between the source region and the drain region. The device includes a first conductive trench extending through, and electrically insulated from, the second structural region on one side of the gate electrode; and a second conductive trench extending through the source region, the body region, and right through the second structural region on an opposite side of the gate electrode, electrically insulated from the second structural region and electrically coupled to the body region and to the source region.
Abstract: A wafer-level packaging, comprising: a first semiconductor body integrating a MEMS structure; a second semiconductor body, including a surface electrical-contact region and an ASIC coupled to the MEMS structure and to said electrical-contact region; a first coating layer, made of resin, which englobes and protects the first body, the second body, and the electrical-contact region; at least one first conductive through via, which extends through the first coating layer in an area corresponding, and electrically coupled, to the first electrical-contact region; an electrical-contact pad, which extends over the first coating layer, electrically coupled to the first conductive through via; a third semiconductor body, integrating an electronic circuit, glued on the first coating layer; a second coating layer, made of resin, which englobes and protects the third body; at least one second conductive through via, which extends completely through the second coating layer in an area corresponding, and electrically coupl
Abstract: An embodiment for encoding digital images includes: partitioning the images into image blocks, subjecting the image blocks to transform into the frequency domain, and, possibly after thresholding resulting in lossy encoding, subjecting the image blocks transformed into the frequency domain to variable length coding to produce compressed encoded image blocks. Transform into the frequency domain may be, e.g., via wavelet transform, such as Haar wavelet transform, and variable length coding may be via Exponential-Golomb codes. An embodiment may also be adapted for transferring picture data over a bus in a system such as, e.g., a System-on-Chip (SoC) by generating compressed encoded image blocks for transfer over the bus and decoding compressed encoded image blocks transferred over the bus.
Abstract: An embodiment relates to a method for color processing of an input image, the method including the steps of low-pass filtering of the input image to obtain a low-pass component, high-pass filtering of the input image to obtain a high-pass component, processing the input image for edge detection to obtain edginess parameters, and performing a color-space transformation of the input image based on the low-pass component, the high-pass component, and the edginess parameters.
Abstract: A ring oscillator includes a first delay stage generating a first phase signal and a second delay stage generating a second phase signal. Each of the first and second delay stages includes variable resistance circuit. A phase comparator circuit performs a phase comparison between the first and second phase signals to generate a phase error signal. An amplifier circuit generates a control signal from the phase error signal. A feedback loop applies the control signal to control the resistance of the variable resistance circuits in the first and second delay stages.
Abstract: A method of testing integrated circuits, including establishing at least a first physical communication channel between a test equipment and an integrated circuit under test by having at least a first probe of the test equipment contacting a corresponding physical contact terminal of the integrated circuit under test; having the test equipment and the integrated circuit under test exchange, over said first physical communication channel, at least two signals selected from the group including at least two test stimuli and at least two test response signals, wherein said at least two signals are exchanged by means of at least one modulated carrier wave modulated by the at least two signals.
Abstract: An embodiment solution for operating a non-volatile memory of a complementary type is proposed. The non-volatile memory includes a plurality of sectors of memory cells, each memory cell being adapted to take a programmed state or an erased state. Moreover, the memory cells are arranged in locations each formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively.
Type:
Grant
Filed:
October 24, 2013
Date of Patent:
September 13, 2016
Assignee:
STMicroelectronics S.r.l.
Inventors:
Marcella Carissimi, Marco Pasotti, Fabio De Santis
Abstract: An integrated magnetoresistive device, where a substrate of semiconductor material is covered, on a first surface, by an insulating layer. A magnetoresistor of ferromagnetic material extends in the insulating layer and defines a sensitivity plane of the sensor. A concentrator of ferromagnetic material including at least one arm, extending in a transversal direction to the sensitivity plane and vertically offset to the magnetoresistor. In this way, magnetic flux lines directed perpendicularly to the sensitivity plane are concentrated and deflected so as to generate magnetic-field components directed in a parallel direction to the sensitivity plane.
Type:
Grant
Filed:
December 23, 2011
Date of Patent:
September 13, 2016
Assignee:
STMicroelectronics S.r.l.
Inventors:
Dario Paci, Marco Morelli, Caterina Riva
Abstract: A frequency doubling device suitable to generate an output terminal voltage oscillating at a differential frequency double the frequency of the input differential voltage, includes a first differential pair of P-type transistors and a second differential pair of N-type transistors controlled by the differential input voltage, as well as an LC oscillator including a LC resonant dipole through which the absorbed current is forced by two differential pairs of transistors.
Abstract: A transmission channel transmits high-voltage pulses and receives echos of the high-voltage pulses. The transmission channel includes a buffer with anti-memory circuitry to couple drains of the buffer transistors to voltage reference terminals during a clamping phase.
Abstract: An embodiment of a measuring circuit for measuring the leakage current flowing in a portion of an electronic device when said portion is biased by a biasing unit of the electronic device is proposed. The measuring circuit includes a first section configured to generate a threshold current, a second section configured to receive the leakage current, a third section configured to compare the threshold current with the leakage current, and a fourth section configured to generate an output voltage based on the comparison between the threshold current and the leakage current. Said first section is configured to set the value of said threshold current to a different value at each reiteration of an operating cycle. Said fourth section is configured to measure said leakage current based on a detection of a change in the value of the output voltage between two reiterations of the operating cycle.