Abstract: A proximity sensor may include an array of Geiger mode avalanche photodiodes, each including an anode contact and a cathode contact. A common cathode contact may be coupled to the cathode contacts of the array to define a first connection lead at a back side of the array. A common anode collecting grid contact may be coupled to the anode contacts of the array to define a second connection lead of the array. Circuitry may be coupled with the first and second connection leads and configured to sense at least one of a dark current and a rate of current spikes generated in dark conditions, and generate an output signal representing an estimated distance of an object from the array upon the sensing.

Abstract: A base carries a first chip and a second chip oriented differently with respect to the base and packaged in a package. Each chip integrates an antenna and a magnetic via. A magnetic coupling path connects the chips, forming a magnetic circuit that enables transfer of signals and power between the chips even if the magnetic path is interrupted, and is formed by a first stretch coupled between the first magnetic-coupling element of the first chip and the first magnetic-coupling element of the second chip, and a second stretch coupled between the second magnetic-coupling element of the first chip and the second magnetic-coupling element of the second chip. The first stretch has a parallel portion extending parallel to the faces of the base. The first and second stretches have respective transverse portions extending on the main surfaces of the second chip, transverse to the parallel portion.

Abstract: A method controls a power factor correction converter that includes a boost inductor and a switch. The method generates a sense signal representing a rectified AC input voltage or an inductor current through the boost inductor, turns on the switch in response to determining, based on the sense signal, a zero current condition through the boost inductor, turns off the switch after an on-time interval, generates a feedback signal based on an output voltage of the converter, and compares the feedback signal with a threshold. If the feedback signal is smaller than the threshold, the method generates a command signal, representing a phase domain including 0 and ?, based on the feedback signal and the power threshold, and keeps the switch off when a phase of the input rectified AC voltage or of the inductor current is in the phase domain even if the zero current condition has been determined.

Abstract: A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.

Abstract: PDs that can be supplied through the LAN line are discriminated from PDs that cannot be so supplied as a function of the resistance of the supply line and of the voltage drop caused by nonlinear elements in series therewith. The values of these two parameters are estimated by applying two distinct voltages to the supply terminals of the LAN line and sensing the relative steady-state currents absorbed by the power supply line, and by processing voltage and current values for estimating the resistance of the line and the voltage drop caused by nonlinear elements connected in series therewith.

Abstract: A specimen holder is configured to hold, during a sample preparation procedure carried out using first and second sample preparation apparatuses, a semiconductor device to be analyzed using an electron microscope. The specimen holder includes a holding portion having a support configured to support the semiconductor device; and a supporting portion configured to releasable support the holding portion. The supporting portion includes an engaging element configured to couple the specimen holder into the first and second sample preparation apparatuses during the sample preparation procedure, and a guide configured to enable the holding portion to slide within the guide and vary a position of the holding portion with respect to the supporting portion.

Abstract: An embodiment described herein includes a method for producing a wafer of a first semiconductor material. Said first semiconductor material has a first melting temperature. The method comprises providing a crystalline substrate of a second semiconductor material having a second melting temperature lower than the first melting temperature, and exposing the crystalline substrate to a flow of first material precursors for forming a first layer of the first material on the substrate. The method further comprising bringing the crystalline substrate to a first process temperature higher than the second melting temperature, and at the same time lower than the first melting temperature, in such a way the second material melts, separating the second melted material from the first layer, and exposing the first layer to the flow of the first material precursor for forming a second layer of the first material on the first layer.

Abstract: An electric contact structure includes a first structural layer; a second structural layer made of dielectric material extending over the first structural layer; and an intermediate layer made of conductive material extending between the first structural layer and the second structural layer. A trench extends in the second structural layer delimited laterally by a wall of the second structural layer and at the bottom by a surface region of the intermediate layer. A diffusion barrier extends in the trench covering the surface region of the intermediate layer and the wall of the second structural layer. The diffusion barrier is a TiW—TiN—TiW tri-layer.

Abstract: A stack of chips is formed by a first integrated-circuit chip and a second integrated-circuit chip. The chips have opposing faces which are separated from each other by an interposed spacer. The spacer is fastened by adhesion to only one of the opposing faces. The opposing faces are fastened to each other by a local adhesive which is separate from spacer.

Abstract: The operation of a circuit exhibiting a delay that is subject to a time spread as a function of process, voltage, and temperature variations is synchronized with a synchronization signal. A digital delay corresponding to the time spread is applied to the synchronization signal. The digital delay is generated via cascaded delay elements having respective delay values and by controlling the number of cascaded delay elements in the circuit that are applied to the synchronization signal.

Abstract: A control device controls a switching circuit of a DC-DC converter. The switching circuit includes a half-bridge with at least first and second switches connected between an input voltage and a reference voltage. The converter comprises a transformer with a primary coupled with the center point of the half-bridge and a secondary coupled with a load. The control device comprises an error detector configured to determine an error signal representing a difference between a first signal representative of the voltage across the load and a first reference signal and a frequency controller configured to increase the switching frequency of the half-bridge when the error signal is kept below a second signal.

Abstract: An integrated control circuit of a switch is described, which is adapted to open or close a current path; said integrated circuit includes a comparator to compare a first signal with a second signal representative of the current flowing through said current path. The comparator outputs a third variable signal between a low logic level and a high logic level according to whether said second signal is lower than said first signal or vice versa; the integrated circuit has a driver to generate a signal to drive said switch in response to the third signal, and is configured to detect a spike on the leading edge of said second signal and to blank said third signal for a first blanking time period which depends on a turn-on delay of said switch and a second blanking period which depends on the duration of said spike on the leading edge of said second signal.

Abstract: A microfluidic device, comprising: a semiconductor body, having a first side and a second side, opposite to one another in a first direction; and at least one well, configured for containing a fluid, extending in the semiconductor body starting from the first side and being delimited at the bottom by a bottom surface. The microfluidic device further comprises a stirring structure integrated in the well at the bottom surface, the stirring structure including a first stirring portion coupled to the semiconductor body and provided with at least one first suspended beam configured for being moved in a second direction so as to generate, in use, agitation of the fluid present in said well.

Abstract: The present invention relates to a method and a circuit for testing a tweeter. The tweeter is part of a loudspeaker system. The method includes the steps of: applying a high-frequency voltage signal to one terminal of the tweeter, whereby the high-frequency voltage signal is generated by first electronic means. The method also includes applying a constant voltage signal to the other terminal of the tweeter, whereby the constant voltage signal is generated by second electronic means. The method includes measuring a current (Iload) that flows through the tweeter into the second electronic means and determining a connect/disconnect state of the tweeter from the value of the current.

Abstract: To apply an anti-wetting coating to a substrate of a semiconductor material, a method includes applying to a support a solution of a hydrocarbon comprising at least one unsaturated bond and, optionally, at least one hetero-atom for obtaining a layer of hydrocarbons. The method also includes treating at least one surface of the substrate of the semiconductor material with an acid. The layer of hydrocarbons is transferred from the support to the surface of the substrate of the semiconductor material. The layer of hydrocarbons is chemically coupled with the surface of the substrate of the semiconductor material.

Abstract: An image processing system includes a first processor that acquires frames of image data. For each frame of data, the first processor generates a Gaussian pyramid for the frame of data, extract histogram of oriented gradient (HOG) descriptors for each level of the Gaussian pyramid, compresses the HOG descriptors, and sends the compressed HOG descriptors. A second processor is coupled to the first processor and is configured to receive the compressed HOG descriptors, aggregate the compressed HOG descriptors into windows, compare data of each window to at least one stored model, and generate output based upon the comparison.

Abstract: An estimate of the initial position of a rotor is made by monitoring sensed motor current signals which are amplitude and phase modulated with the rotor flux position in response to a high frequency voltage signal injection. The motor current signals are envelope detected to determine zero crossing points. Samples are taken of the motor current signals at positive and negative offsets from the zero crossing point, with the samples processed to identify a direction of the rotor flux axis. Further samples of at least one motor current signal are taken with respect to a certain phase reference, and the samples compared to resolve a polarity of the rotor flux axis which is indicative of the angular position of the rotor.

Abstract: An intra-board chip-to-chip optical communications system has a high bit rate and high data throughput based on the use of a silicon photonic interposer. The system includes a multi-substrate electro-optical structure for communications with CMOS and/or BiCMOS IC chips of a PCB. The structure includes a multi-chip module primary substrate mounted over the supporting PCB. The multi-chip module primary substrate implements high frequency electrical interconnections between transceiver circuit chips, mounted on the silicon photonic interposer, and the IC chips.

Abstract: Capacitance sensing circuits and methods are provided. The capacitance sensing circuit includes a capacitance-to-voltage converter configured to receive a signal from a capacitance to be sensed and to provide an output signal representative of the capacitance, an output chopper configured to convert the output signal of the capacitance-to-voltage converter to a sensed voltage representative of the capacitance to be sensed, an analog accumulator configured to accumulate sensed voltages during an accumulation period of NA sensing cycles and to provide an accumulated analog value, an amplifier configured to amplify the accumulated analog value, and an analog-to-digital converter configured to convert the amplified accumulated analog value to a digital value representative of the capacitance to be sensed. The analog accumulator may include a low pass filter having a frequency response to filter wideband noise.

Abstract: A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network.