Abstract: A scalar multiplication operation includes an iterative procedure performing a set of operations at each iteration on a bit or on a group of consecutive bits of a secret key. The multiplication operation includes multiplying values of projective format coordinates by a random value. The random value is a product of a random number generated over a range having as end value a first value, with a second value, which is larger than said first value. The first value is a power of two of a word size multiplied by a multiplier value, minus one. The second value is equal to a power of two of a number of bits of the coordinates divided by the first value. The multiplier value is an integer greater than or equal to one and smaller than a ratio of said number of bits to the word size.

Abstract: A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.

Abstract: A method for manufacturing a device for ejecting a fluid, including the steps of: forming, in a first semiconductor wafer that houses a nozzle of the ejection device, a first structural layer; removing selective portions of the first structural layer to form a first portion of a chamber for containing the fluid; removing, in a second semiconductor wafer that houses an actuator of the ejection device, selective portions of a second structural layer to form a second portion of the chamber; and coupling together the first and second semiconductor wafers so that the first portion directly faces the second portion, thus forming the chamber. The first portion defines a part of volume of the chamber that is larger than a respective part of volume of the chamber defined by the second portion.

Abstract: The present disclosure relates to a method and device for performing an elliptic curve cryptography computation comprising: twisting, by a first device based on a first index of quadratic or higher order twist (d), a first point (P?KB) on a first elliptic curve over a further elliptic curve twisted with respect to the first elliptic curve to generate a twisted key (PKB); transmitting the twisted key (PKB) to a further device; receiving, from the further device, a return value (ShS) generated based on the twisted key (PKB); and twisting, by the first device based on the first index of quadratic or higher order twist (d), the return value (ShS) over the first elliptic curve to generate a result (ShS?) of the ECC computation.

Abstract: A control circuit for a multiphase buck converter includes a regulator circuit and a plurality of phase control circuits. The regulator circuit generates a regulation signal based on a feedback signal and a reference signal, and each phase control circuit receives a current sense signal and generates a respective PWM signal based on the respective current sense signal and the regulation signal. The control circuit includes a first selector circuit and a second selector circuit configured to receive a selection signal and selectively connect each phase control circuit of a subset of the phase control circuits to a PWM signal for driving a respective stage of the multiphase buck converter, and to a current sense signal provided by the respective stage of the multiphase buck converter. A selection control circuit generates the selection signal in order to connect the phase control circuits to different stages of the multiphase buck converter.

Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

Abstract: A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.

Abstract: A microfluidic group includes a female connector and a male needle connector. The female connector has a connector chamber in a containment body; a duct extending in the containment body to a duct opening on a first face of the connector chamber; a needle entry hole extending from a lateral face of the containment body to a second face, not facing the first face of the connector chamber; and a gasket arranged in the connector chamber. The gasket has a side wall internally delimiting a cavity and extending in part adjacent to the second face of the connector chamber. The cavity of the gasket faces the first face of the connector chamber.

Abstract: The present disclosure relates to a method for controlling a device comprising an oscillation circuit, configured to provide a clock signal to a radio frequency circuit, and an antenna, in which the enabling of the passage of the signal from the circuit to the antenna is delayed with respect to an instant from which a power amplifier of the circuit is enabled.

Abstract: A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius.

Abstract: A semiconductor device, such as a QFN (Quad-Flat No-lead) package, includes an insulating encapsulation of a semiconductor chip. The insulating encapsulation is formed by a first encapsulation material which encapsulates the semiconductor chip and a second encapsulation material that is molded onto an upper surface of the first encapsulation material. The first encapsulation material includes an oblique cavity extending from the upper surface. The second encapsulation material includes an anchoring protrusion that enters into the cavity.

Abstract: A substrate includes electrically-conductive tracks. A semiconductor chip is arranged on the substrate and electrically coupled to selected ones of the electrically-conductive tracks. Containment structures are provided at selected locations on the electrically-conductive tracks, where the containment structures have respective perimeter walls defining respective cavities. Each cavity is configured to accommodate a base portion of a pin holder. These pin holders are soldered to the electrically-conductive tracks within the cavities defined by the containment structures. Each containment structure may be formed by a ring of resist material configured to receive solder and maintain the pin holders in a desired alignment position.

Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

Abstract: A process for manufacturing a microelectromechanical mirror device includes, in a semiconductor wafer, defining a support frame, a plate connected to the support frame so as to be orientable around at least one rotation axis, and cantilever structures extending from the support frame and coupled to the plate so that bending of the cantilever structures causes rotations of the plate around the at least one rotation axis. The process further includes forming piezoelectric actuators on the cantilever structures, forming pads on the support frame, and forming spacer structures protruding from the support frame more than both the pads and the stacks of layers forming the piezoelectric actuators.

Abstract: A microfluidic dispenser device of inhalable substances includes a casing, housed in which are a driving circuit and a microfluidic cartridge having a tank that contains a liquid to be delivered. The microfluidic cartridge is provided with at least one nebulizer controlled by the driving device. The nebulizer includes: a substrate; a plurality of chambers formed on the substrate and fluidically coupled to the tank for receiving the liquid to be delivered; and a plurality of heaters, which are formed on the substrate in positions corresponding to respective chambers, are thermally coupled to the respective chambers and are separated from the respective chambers by an insulating layer, and are controlled by the driving device. Each chamber is fluidically connected with the outside by at least one respective nozzle.

Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.

Abstract: An electronic device such as a hardware security module device comprises a first cryptographic processing circuit configured to receive input data packets and apply thereto a first cryptographic processing to provide output data packets. A second cryptographic processing circuit is provided in the device, configured to receive the output data packets, apply thereto a second cryptographic processing inverse to the first cryptographic processing, and provide comparison data packets as a result of applying the second cryptographic processing to the output data packets received. A comparison processing circuit in the device is configured to compare the input data packets with the comparison data packets, and to produce an error signal as a result of the input data packets being different from the comparison data packets.

Abstract: A negative impedance circuit includes: a differential circuit stage; a positive feedback path from an output of the differential circuit stage to a first input of the differential circuit stage; and a negative feedback path from the output of the differential circuit stage to a second input of the differential circuit stage. The negative feedback path includes a first transistor, and a unitary gain path from the output of the differential circuit stage to the second input of the differential circuit stage, the unitary gain path coupled to ground via a reference impedance. The positive feedback path includes a second transistor. The first and second transistors are coupled in a current mirror arrangement and have respective control electrodes configured to be driven by the output of the differential circuit stage, where the negative impedance circuit causes a negative impedance at the first input of the differential circuit stage.

Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.