Abstract: The sensor is configured to provide a digital output signal and has a digital detector, which is configured to detect a physical quantity and generate a conditioned digital signal indicative of the detected physical quantity; and a rate modification stage, configured to receive the conditioned digital signal and a group of parameters, the group of parameters comprising an interpolation factor and a downsampling factor, and to provide the digital output signal. The rate modification stage has an interpolator and a decimation element. The interpolator is configured to receive and to upsample the conditioned digital signal based on the interpolation factor and to provide an interpolated signal. The decimation element is configured to downsample the interpolated signal based on the downsampling factor, thereby generating the digital output signal.

Abstract: A sensor includes detection circuitry and control circuitry coupled to the detection circuitry. The detection circuitry generates a detection signal indicative of a detected physical quantity. The control circuitry, in operation receives the detection signal and a frequency-indication signal, and generates a trigger signal based on the frequency-indication signal and a set of local reference signals. The sensor generates a digital output signal and a locking signal based on the trigger signal and the detection signal. The generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal. The locking signal is temporally aligned with the digital output signal.

Abstract: A connecting strip of conductive elastic material having an arched shape having a concave side and a convex side. The connecting strip is fixed at the ends to a support carrying a die with the convex side facing the support. During bonding, the connecting strip undergoes elastic deformation and presses against the die, thus electrically connecting the at least one die to the support.

Abstract: A method for the personalization of an integrated circuit card, includes: simulating a downloading of a single image corresponding to a fixed part of personalization data of the integrated circuit card; simulating an execution of a sequence of personalization commands for the integrated circuit card to generate a set of personalization data; combining the set of personalization data with the single image to obtain a card image comprising the fixed part of personalization data and the set of personalization data; encrypting the card image to obtain an encrypted single image; and downloading the encrypted single image in a memory of the integrated circuit card.

Abstract: An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

Abstract: A method, includes: storing at least one set of data in a memory space, wherein the at least one set of data stored has a memory footprint in the memory space; and coupling, to the at least one set of data, a respective counter indicative of the at least one set of data, wherein the respective counter is embedded in the at least one set of data without increasing the memory footprint in the memory space.

Abstract: An embodiment pulse-width modulation (PWM) modulator circuit comprises a first half-bridge stage having a first output node and a second half-bridge stage having a second output node. The first output node and the second output node are configured to have an electrical load coupled therebetween to apply thereto a PWM-modulated output signal. The circuit comprises a differential stage having input nodes configured to receive an input signal applied between the input nodes and produce a differential control signal for the first half-bridge stage and the second half-bridge stage. A current comparator is arranged intermediate the differential stage and the first and second half-bridge stages. The current comparator is configured to produce a PWM-modulated drive signal to drive the half-bridge stages as a function of the input signal applied between the input nodes in the differential stage.

Abstract: In accordance with an embodiment, a detection device includes: an infrared temperature sensor configured to provide a temperature signal associated with an heat emission of at least one individual within a monitored area; an electrostatic-charge-variation sensor configured to provide a charge-variation signal indicative of a variation of electrostatic charge associated with the at least one individual; and a processing unit, coupled to the infrared temperature sensor and to the electrostatic-charge-variation sensor, the processing unit configured to detect a presence of the at least one individual within the monitored area by receiving the temperature signal and the charge-variation signal, and jointly processing the temperature signal and charge.

Abstract: Leadframes for semiconductor devices are manufactured by providing a laminar substrate of laser direct structuring material, the laminar substrate comprising first and second opposed surfaces, applying laser beam processing to the substrate to provide a first pattern of electrically-conductive formations at the first surface, a second pattern of electrically-conductive formations at the second surface and electrically-conductive vias through the substrate between the first surface and the second surface. Electrically-conductive material is formed, for instance via electrolytic or electroless growth of electrically-conductive material such a copper onto the first and second pattern of electrically-conductive formations as well as onto the electrically-conductive vias provided by applying laser beam processing to the substrate.

Abstract: In an embodiment, a method for shaping a PWM signal includes: receiving an input PWM signal; generating an output PWM signal based on the input PWM signal by: when the input PWM signal transitions with a first edge of the input PWM signal, transitioning the output PWM signal with a first edge of the output PWM signal; and when the input PWM signal transitions with a second edge before the first edge of the output PWM signal transitions, delaying a second edge of the output PWM signal based on the first edge of the output PWM signal.

Abstract: Methods, microprocessors, and systems are provided for implementing an artificial neural network. Data buffers in virtual memory are coupled to respective processing layers in the artificial neural network. An ordered visiting sequence of layers of the artificial neural network is obtained. A virtual memory allocation schedule is produced as a function of the ordered visiting sequence of layers of the artificial neural network, the schedule including a set of instructions for memory allocation and deallocation operations applicable to the data buffers. A physical memory configuration dataset is computed as a function of the virtual memory allocation schedule for the artificial neural network, the dataset including sizes and addresses of physical memory locations for the artificial neural network.

Abstract: An embodiment phase-change memory device includes a memory array provided with a plurality of phase-change memory cells, each having a body made of phase-change material and a first state, in which the phase-change material is completely in an amorphous phase, and at least one second state, in which the phase-change material is partially in the amorphous phase and partially in a crystalline phase. A programming-pulse generator applies to the memory cells rectangular dynamic-programming pulses having an amplitude and a duration calibrated for switching the memory cells from the first state to the second state.

Abstract: A cell includes a first pair and a second pair of MOS transistors. Each of the first pair and second pair of MOS transistors have drain electrodes coupled to a respective common input node. Each of the first pair and second pair of MOS transistors includes a diode-connected MOS transistor and a latched MOS transistor. The latched MOS transistors of the first pair and second pair of MOS transistors have cross-coupled gate and drain electrodes. Source electrodes of the diode connected MOS transistors from the first pair and second pair of MOS transistors are coupled to a first current output common node to output a current to a first current collecting circuit. Source source electrodes of the latched MOS transistors of the first pair and second pair of MOS transistors are coupled to a second current output common node to output a current to a second current collecting circuit.

Abstract: A method of operating an electronic converter is provided in which a switching activity of a switching stage of the electronic converter is active or inactive based on a control signal, and the method includes operating the electronic converter, alternatively, in a first or a second mode. In the first mode, the status signal is initially asserted and is de-asserted in response to an amplitude of the input sensing signal failing to reach a first reference threshold value. In the second mode, the status signal is initially de-asserted and an auxiliary power supply signal is periodically varied with a variation period. After a time interval equal to the variation period, a comparison signal is asserted in response to an amplitude of the sensed signal reaching a second reference threshold value. The status signal is asserted based on conditions of the comparison signal and the periodically varying auxiliary power supply signal.

Abstract: A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down.

Abstract: A configurable voltage regulating circuit includes first through fourth switches. A flying capacitor is coupled between a common mode node and a pump node, and a sense resistance network is coupled between an output node and an input of an error amplifier and configured to provide a sensed output voltage. The error amplifier receives at another input a reference voltage and generates an error signal. A charging circuit supplies a charging current to the pump node, and controls the value of the charging current as a function of the error signal. A switch command signals generator generates respective first, second, third, and fourth switch signals to control the first switch, second switch, third switch, and fourth switch. The generator sets the configurable voltage regulating circuit as either a charge pump or a linear regulator based the input voltage being less than a first threshold or greater than a second threshold.

Abstract: A set of configuration memory locations store configuration data for a microcontroller unit. A hardware monitoring module is coupled by an interconnection bus to the configuration memory locations. The hardware monitoring module reads from an instruction memory a command including an address of a target memory location in the set of configuration memory locations. Data is read from the target memory location corresponding to the address read and a checksum value is computed as a function of the data that is read from the target memory location. The computed checksum value is then compared to a respective expected checksum value stored in a checksum storage unit. An alarm signal is triggered in response to a mismatch detected between the computed checksum value and the respective expected checksum value.

Abstract: A sensor is driven at a first heating power value. The sensor generates a sensing signal that is indicative of a sensed entity. A possible onset of a sensor contamination condition is detected as a function of the sensing signal generated by the sensor. If such detecting fails to indicate onset of a sensor contamination condition, the sensor continues to be driven at the first heating power value. However, if such detecting indicates onset of a sensor contamination condition, a protection mode is activated. In the protection mode, the sensor is driven at a second heating power value for a protection interval, where the second heating power value is lower than the first heating power value. Furthermore, the operation may refrain from supplying power to the sensor for a further protection interval, wherein the further protection interval is longer than the protection interval.

Abstract: A control circuit for controlling a switching stage of an electronic converter includes a first terminal configured to provide a drive signal and a second terminal configured to receive a first feedback signal. A third terminal receives a second feedback signal and a driver circuit provides the drive signal as a function of a PWM signal. A PWM signal generator circuit generates the PWM signal as a function of the first feedback signal, a reference threshold and the second feedback signal or a slope compensation signal. The control circuit is configured to sense an input signal, provide a first compensation parameter, and provide a first compensating signal as a function of a power of the input sensing signal.

Abstract: A process for manufacturing MEMS devices, includes forming a first assembly, which comprises: a dielectric region; a redistribution region; and a plurality of unit portions. Each unit portion of the first assembly includes: a die arranged in the dielectric region; and a plurality of first and second connection elements, which extend to opposite faces of the redistribution region and are connected together by paths that extend in the redistribution region, the first connection elements being coupled to the die. The process further includes: forming a second assembly which comprises a plurality of respective unit portions, each of which includes a semiconductor portion and third connection elements; mechanically coupling the first and second assemblies so as to connect the third connection elements to corresponding second connection elements; and then removing at least part of the semiconductor portion of each unit portion of the second assembly, thus forming corresponding membranes.