Patents Assigned to STMicroelectronics S.r.l.
  • Patent number: 12144077
    Abstract: An LED lighting system includes switching circuitry adjustably driving a string of LEDs and being controlled by a reference current and an enable signal. A controller generates the reference current and enable signal based upon a PWM signal such that the switching circuitry: sources a first LED current to the string of LEDs that is proportional to a duty cycle of the PWM signal when the duty cycle is greater than a threshold duty cycle to thereby perform analog dimming; and sources a second LED current to the string of LEDs that has a duty cycle proportional to the duty cycle of the PWM signal when the duty cycle of the PWM signal is less than the threshold duty cycle, such that an average LED current delivered to the string of LEDs is proportional to the duty cycle of the PWM signal to thereby perform digital dimming.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: November 12, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giovanni Gritti, Claudio Adragna
  • Publication number: 20240371738
    Abstract: A packaged semiconductor device includes a substrate having a first surface and a second surface opposite the first surface. At least one semiconductor die is mounted at the first surface of the substrate. Electrically-conductive leads are arranged around the substrate, and electrically-conductive formations couple the at least one semiconductor die to selected leads of the electrically-conductive leads. A package molding material is molded onto the at least one semiconductor die, onto the electrically-conductive leads and onto the electrically-conductive formations. The package molding material leaves the second surface of the substrate uncovered by the package molding material. The substrate is formed by a layer of electrically-insulating material.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventor: Roberto TIZIANI
  • Patent number: 12135679
    Abstract: In an embodiment a system on chip includes at least one master device, at least one slave device, a connection interface configured to route signals between the at least one master device and the at least one slave device, the connection interface configured to operate according to configuration parameters, and a configuration bus connected to the connection interface, wherein the configuration bus is configured to deliver new configuration parameters to the connection interface so as to adapt operation of the connection interface.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: November 5, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonino Mondello, Salvatore Pisasale
  • Patent number: 12135572
    Abstract: In an embodiment, a method includes: providing a voltage setpoint to a voltage converter; generating an output voltage at a voltage rail with the voltage converter based on the voltage setpoint; when the voltage setpoint is transitioning from a first voltage setpoint to a second voltage setpoint that has a lower magnitude than the first voltage setpoint, providing a first constant current to a first node coupled to a control terminal of an output transistor to turn on the output transistor, where the output transistor includes a source terminal coupled to a first terminal of a first resistor, and where a current path of the output transistor is coupled to the voltage rail; and turning off the output transistor after the output voltage reaches the target output voltage corresponding to the second voltage setpoint.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: November 5, 2024
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alberto Cattani, Alessandro Gasparini, Stefano Ramorini
  • Patent number: 12135668
    Abstract: A processor includes a synchronous circuit including a plurality of processing stages, wherein each processing stage includes a selection data bus; and an asynchronous circuit coupled to each selection data bus, wherein the asynchronous circuit includes an asynchronous state machine whose states correspond to a process phase or a plurality of circuits, wherein the asynchronous circuit further includes a selectable delay circuit whose delay is determined by a present state of the asynchronous state machine, and wherein the asynchronous circuit is configured for generating a plurality of processing stage clock signals each having a selectable delay provided by the selectable delay circuit.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: November 5, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Castellano, Francesco Bruni, Luca Gandolfi, Marco Leo
  • Patent number: 12135351
    Abstract: An integrated circuit (IC) includes: a first functional analog pin or pad; a first analog test bus coupled to the first functional analog pin or pad; first and second analog circuits coupled to the first analog test bus; and a test controller configured to: when the IC is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus so that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keep disconnected an input or output of the second analog circuit from the first analog test bus, and when the IC is in a test mode, selectively connect the input or output of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: November 5, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Filippo Colombo
  • Patent number: 12134556
    Abstract: A semiconductor device includes: a substrate; a transduction microstructure integrated in the substrate; a cap joined to the substrate and having a first face adjacent to the substrate and a second, outer, face; and a channel extending through the cap from the second face to the first face and communicating with the transduction microstructure. A protective membrane made of porous polycrystalline silicon permeable to aeriform substances is set across the channel.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: November 5, 2024
    Assignees: STMICROELECTRONICS S.R.L., STMicroelectronics International N.V.
    Inventors: Enri Duqi, Lorenzo Baldo, Paolo Ferrari, Benedetto Vigna, Flavio Francesco Villa, Laura Maria Castoldi, Ilaria Gelmi
  • Patent number: 12136883
    Abstract: An active flyback converter is transitioned between a plurality of operational states based on a comparison of a control voltage signal to voltage thresholds and a count of a number of consecutive switching cycles during which a clamp switch is kept off. The plurality of operational states includes a run state, an idle state, a first burst state, and a second burst state. Each set of consecutive switching cycles of the first burst state includes a determined number of switching cycles during which signals are generated to turn the power switch on and off and to maintain an off state of the clamp switch, and a switching cycle in a determined position in the set of switching cycles during which signals are sequentially generated to turn the power switch on, turn the power switch off, turn the clamp switch on and turn the clamp switch off.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: November 5, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Claudio Adragna, Massimiliano Gobbi, Giuseppe Bosisio
  • Patent number: 12132413
    Abstract: A converter circuit converts an input signal applied across a first and a second input node into a converted output signal across a first and a second output node. The converter circuit includes a switching network coupled to the first input node via an inductor having a current flowing therethrough. In a hysteresis current control mode of the switching network, the current flowing through the inductor has a triangular waveform with rising and falling edges between a first current threshold and a second current threshold alternating with a switching frequency. The switching frequency is controlled by varying the distance between the first current threshold and the second current threshold.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: October 29, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Sebastiano Messina, Marco Torrisi
  • Patent number: 12132487
    Abstract: In start-up, current is sourced by a current source to a first plate of a first capacitor while a second capacitor is maintained at zero charge. In a subsequent first operating phase, current is sourced to a first plate of the second capacitor while a second plate of the first capacitor is connected to the first plate of the second capacitor. At the end of the first operating phase, the first capacitor is discharged. In a subsequent second operating phase, current is sourced to the first plate of the first capacitor while a second plate of the second capacitor is connected to the first plate of the first capacitor. At the end of the second operating phase, the second capacitor is discharged. Steady state operation of the circuit involves an alternation of the first and second operating phases interleaved with transition phases where the first and second capacitors are discharged.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: October 29, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Pinsero, Marco Attanasio, Alberto Cattani
  • Patent number: 12130319
    Abstract: A device that provides high impedance contact pads for an electrostatic charge sensor. The contact pads are shared between the electrostatic charge sensor and drivers. The contact pads are set to a high impedance state by reducing current leakage through the drivers. Compared to electrostatic charge sensor with low impedance contact pads, the electrostatic charge sensor disclosed herein has high sensitivity, and is able to detect weak electrostatic fields.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: October 29, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Massimo Orio
  • Patent number: 12132815
    Abstract: A method includes providing a reference clock signal having a reference period, providing a sampling clock signal having a sampling clock period shorter than the reference period of the reference clock signal, measuring the first subperiod as a first ratio of the first subperiod to the period of the sampling clock signal, measuring the second subperiod as a second ratio of the second subperiod to the period of the sampling clock signal, detecting a starting edge of a clock signal having a clock period greater than the reference period, producing a reconstructed reference signal based on the first ratio, the second ratio, and the detected starting edge, comparing the clock period of the clock signal with a period of the reconstructed reference signal to obtain a differential signal indicating a difference therebetween, and providing the differential signal to user circuitry for calibrating the clock signal.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: October 29, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Riccardo Condorelli, Antonino Mondello, Michele Alessandro Carrano
  • Patent number: 12130360
    Abstract: In accordance with an embodiment, an ultrasound transmitter device includes a transformer comprising a secondary winding configured to be coupled to a piezoelectric transducer; a plurality of transistors coupled to the primary winding of the transformer and to a ground terminal via a sense resistor; an amplifier having an output coupled to control nodes of the plurality of transistors, a first input coupled to the sense resistor, and second input coupled to a reference resistor; a switching circuit configured to alternately couple control nodes of the plurality of transistors to an output of amplifier and to a reference node via complementary pulse signals, wherein the switching circuit is configured to turn on and turn off the plurality of transistors and operate the plurality of transistors in a push-pull manner; and a digital-to-analog converter having an output coupled to the reference resistor.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: October 29, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonio Davide Leone, Vanni Poletto
  • Publication number: 20240356443
    Abstract: A time based boost DC-DC converter generates an output voltage using an inductor. A voltage error between the output voltage and a reference voltage is determined and processed in a) an integral control branch which converts the voltage error into an integral control current signal used to control a current controlled oscillator, and b) a proportional branch which converts the voltage error into a proportional control current signal used to control signal a delay line. Current flowing in the inductor is sensed, attenuated and used to apply adjustment to the integral and proportional control current signals. The output from the current controlled oscillator is passed through the delay line and phase detected in order to generate pulse width modulation (PWM) control signaling driving switch operation in the converter.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Alessandro GASPARINI, Alessandro BERTOLINI, Mauro LEONCINI, Massimo GHIONI, Salvatore LEVANTINO
  • Patent number: 12124713
    Abstract: A system-on-chip includes a processor, a memory and a memory interface coupled to the processor and to the memory. The processor, in operation, generates memory access requests. The memory includes one or more physical banks divided into a succession of sectors, each sector having a size equal to a smallest erasable size of the memory. The memory interface, in operation, responds to receiving memory configuration information by storing logical memory bank configuration information in the one or more configuration registers, the logical memory bank configuration information assigning each sector of the one or more physical banks of the memory to a respective logical memory bank of one or more logical memory banks. The memory interface, in operation, controls access to the memory by the processor based on the logical memory bank configuration information stored in the one or more configuration registers.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: October 22, 2024
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco Bombaci, Andrea Tosoni
  • Patent number: 12125803
    Abstract: A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: October 22, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Paolo Crema
  • Patent number: 12125762
    Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: October 22, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Simone Rascuna', Claudio Chibbaro, Alfio Guarnera, Mario Giuseppe Saggio, Francesco Lizio
  • Patent number: 12125933
    Abstract: A device for detecting UV radiation, comprising: a SiC substrate having an N doping; a SiC drift layer having an N doping, which extends over the substrate; a cathode terminal; and an anode terminal. The anode terminal comprises: a doped anode region having a P doping, which extends in the drift layer; and an ohmic-contact region including one or more carbon-rich layers, in particular graphene and/or graphite layers, which extends in the doped anode region. The ohmic-contact region is transparent to the UV radiation to be detected.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: October 22, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Simone Rascuná, Gabriele Bellocchi, Paolo Badalá, Isodiana Crupi
  • Publication number: 20240348249
    Abstract: A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.
    Type: Application
    Filed: April 9, 2024
    Publication date: October 17, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Francesco PINZIN, Alessandro BERTOLINI, Alberto CATTANI
  • Publication number: 20240347495
    Abstract: A semiconductor product includes a layer of semiconductor die package molding material embedding a semiconductor die having a front surface and an array of electrically-conductive bodies such as spheres or balls around the semiconductor die. The electrically-conductive bodies have front end portions around the front surface of the semiconductor die and back end portions protruding from the layer of semiconductor die package molding material. Electrically-conductive formations are provided between the front surface of the semiconductor die and front end portions of the electrically-conductive bodies left uncovered by the package molding material. Light-permeable sealing material can be provided at electrically-conductive formations to facilitate inspecting the electrically-conductive formations via visual inspection through the light-permeable sealing material.
    Type: Application
    Filed: June 24, 2024
    Publication date: October 17, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventor: Fulvio Vittorio FONTANA