Abstract: Power MOS device, in which a power MOS transistor has a drain terminal that is coupled to a power supply node, a gate terminal that is coupled to a drive node and a source terminal that is coupled to a load node. A detection MOS transistor has a drain terminal that is coupled to a detection node, a gate terminal that is coupled to the drive node and a source terminal that is coupled to the load node. A detection resistor has a first terminal coupled to the power supply node and a second terminal coupled to the detection node.

Abstract: A valve module includes a semiconductor body, cavities in the semiconductor body separated from each other by a distance, a cantilever structure suspended over each cavity to enable at least partial closing of the cavity, and a piezoelectric actuator for each cantilever structure. The piezoelectric actuator is configured for use to cause a positive bending of the respective cantilever structure and so modulate a rate of air flow through the valve module.

Abstract: A DC-DC converter includes clock generation circuitry generating first and second clock signals that are out of phase, and a control signal generator generating a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage. Boost circuitry charges an energy storage component during an on-phase and discharges the energy storage component during an off-phase to thereby generate an output voltage. The on-phase and off-phase are set as a function of the switching control signal. Sum voltage generation circuitry generates a ramp voltage in response to an edge of the first clock signal and generates the summed voltage at an edge of the second clock signal. The sum voltage represents a sum of the ramp voltage and a voltage representative of the current flowing in the energy storage component during the on-phase.

Abstract: A device includes a first directional coupler and a second directional coupler. A first arched waveguide forms a first curved optical path between a first output port of the first directional coupler and a first input port of the second directional coupler. The first arched waveguide has an angle of curvature and a radius of curvature. A second arched waveguide has the angle of curvature and the radius of curvature. The first arched waveguide and the second arched waveguide each have a concavity oriented in the same direction. A first straight waveguide is coupled to a second output port of the first directional coupler and a first end of the second arched waveguide. A second straight waveguide is coupled to a second end of the second arched waveguide and a second input port of the second directional coupler.

Abstract: A circuit includes a field effect transistor having a gate driven via a drive signal. The field effect transistor has a drain-source voltage drop indicative of the intensity of a current flowing in the current path through the field effect transistor. The circuit also includes a pair of sensing transistors that include a first sensing field effect transistor arranged with its drain and gate coupled with the drain and the gate of the field effect transistor, respectively, and a second sensing field effect transistor having a gate configured for receiving a replica of the drive signal. The second sensing field effect transistor is arranged with its current path in series with the current path of the first sensing field effect transistor. A sensing signal at a sensing node is indicative of the current intensity flowing in the current path of the field effect transistor.

Abstract: An integrated semiconductor device includes: a MEMS structure; an ASIC electronic circuit; and conductive interconnection structures electrically coupling the MEMS structure to the ASIC electronic circuit. The MEMS structure and the ASIC electronic circuit are integrated starting from a same substrate including semiconductor material; wherein the MEMS structure is formed at a first surface of the substrate, and the ASIC electronic circuit is formed at a second surface of the substrate, vertically opposite to the first surface in a direction transverse to a horizontal plane of extension of the first surface and of the second surface.

Abstract: A stress sensor formed by a membrane plate; a first bonding region arranged on top of the membrane plate; a cover plate arranged on top of the first bonding region, the first bonding region bonding the membrane plate to the cover plate; three-dimensional piezoresistive elements extending across the membrane plate that are embedded in the bonding layer; and planar piezoresistive elements that extend across the membrane plate and are surrounded by and separated from the bonding layer.

Abstract: Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.

Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.

Abstract: Embodiments of the present disclosure are directed to flat no-lead packages with wettable sidewalls or flanks. In particular, wettable conductive layers are formed on the package over lateral portions of the leads and on portions of the package body, which may be encapsulation material. The wettable conductive layers may also be formed on bottom surfaces of the package body and the leads. The wettable conductive layers provide a wettable flank for solder to wick up when the package is mounted to a substrate, such as a PCB, using SMT. In particular, solder that is used to join the PCB and the package wicks up the side of the wettable conductive layers along a side surface of the package. In that regard, the solder is exposed and coupled to the side surface of the package at the wettable conductive layers, thereby allowing for a visual inspection of the solder joints. The wettable conductive layers are formed on the package after the package body has been formed.

Abstract: A current monitoring circuit includes: an output terminal configured to be coupled to a controller; an inverter having an output coupled to the output terminal; a first transconductance amplifier having first and second inputs configured to be coupled across a sense resistive element, and an output coupled to an input of the inverter; and a current generator having a second transconductance amplifier configured to generate a reference current at an output of the current generator based on a reference voltage, the output of the current generator being coupled to the input of the inverter, where the output of the inverter is configured to be in a first state when a load current flowing through the sense resistive element is higher than a predetermined threshold, and in a second state when the load current is lower than the predetermined threshold, and where the predetermined threshold is based on the reference current.

Abstract: A Hall sensor compensation circuit includes an input node configured for receiving a bias signal for a Hall sensor. A bias node provides to the Hall sensor a compensated bias signal. A compensation network coupled between the input node and the bias node has a gain inversely proportional to Hall mobility, ?n?, wherein the Hall sensing signal is temperature-compensated.

Abstract: A multiple-input analog-to-digital converter device includes analog-to-digital converter circuits arranged between input nodes and output nodes. The analog-to-digital converter circuits operate over respective conversion times to provide simultaneous conversion of the analog input signals into respective conversion time signals. A time-to-digital converter circuit includes timer circuitry common to the plurality of analog-to-digital converter circuits. The timer circuitry cooperates with the analog-to-digital converter circuits to convert the conversion time signals into digital output signals at the output nodes.

Abstract: Semiconductor dice are arranged on a substrate such as a leadframe. Each semiconductor die is provided with electrically-conductive protrusions (such as electroplated pillars or bumps) protruding from the semiconductor die opposite the substrate. Laser direct structuring material is molded onto the substrate to cover the semiconductor dice arranged thereon, with the molding operation leaving a distal end of the electrically-conductive protrusion to be optically detectable at the surface of the laser direct structuring material. Laser beam processing the laser direct structuring material is then performed with laser beam energy applied at positions of the surface of the laser direct structuring material which are located by using the electrically-conductive protrusions optically detectable at the surface of the laser direct structuring material as a spatial reference.

Abstract: A sensor includes an accelerometer, which, in operation, generates accelerometer data, and digital signal processing circuitry. The digital signal processing circuitry, in operation, generates, based on the generated accelerometer data, a value indicative of a cosine of an angle between an acceleration vector associated with current accelerometer data and a reference acceleration vector, compares the generated value indicative of the cosine of the angle between the vector associated with current accelerometer data and the reference acceleration vector with one or more thresholds and generates a tilt signal based on the comparison of the generated value indicative of the cosine of the angle between the vector associated with current accelerometer data and the reference acceleration vector with the one or more thresholds. The tilt signal may be used as an interrupt signal to an application processor.

Abstract: An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.

Abstract: A MEMS sensor generates an output multiscale reading signal supplied to a full scale adjustment stage. The full scale adjustment stage includes a signal input configured to receive the reading signal, a saturation assessment block, and a full scale change block. The saturation assessment block is coupled to the signal input and configured to generate a scale increase request signal upon detection of a saturation condition. The full scale change block is coupled to the saturation assessment block and configured to generate a full scale change signal upon reception of the scale increase request signal.

Abstract: A radio-frequency transceiver device includes a transmission circuit generating a transmission signal at a transmission pad connected to a transmission antenna by modulating a radio frequency signal as a function of a control signal. First and second reception circuits receive first and second signals at first and second reception pads connected to first and second reception antennas. The received first and second signals are demodulated via the radio frequency signal to generate first and second demodulated reception signals. A control circuit operates during a reception test phase to generate only the control signal in order to test, as a function of the first and second demodulated reception signals, whether the received first signal corresponds to the received second signal. A reception error signal indicating a reception error is generated when the test indicates that the received first and second reception signals do not correspond.

Abstract: A device includes image generation circuitry and a convolutional neural network. The image generation circuitry, in operation, generates a binned representation of a wafer defect map (WDM). The convolutional-neural-network, in operation, generates and outputs an indication of a root cause of a defect associated with the WDM based on the binned representation of the WDM and a data-driven model associating WDMs with classes of a defined set of classes of wafer defects.

Abstract: A capacitive sensor for monitoring stresses acting in a construction structure and having a multi-layer structure provided with an upper conductive layer defining an upper outer surface of the sensor. A lower conductive layer defines a lower outer surface. At least a first structural layer of insulating material is in contact with the upper conductive layer and at least a second structural layer of insulating material is in contact with the lower conductive layer. At least a first plate layer of conductive material and at least a second plate layer, of conductive material, and at least one dielectric layer is interposed between the first plate layer and the second plate layer to define at least one detection capacitor inside the multi-layer structure of the sensor. The upper and lower conductive layers jointly defining an electromagnetic screen for screening the detection capacitor against electromagnetic interference originating from outside the capacitive sensor.