Patents Assigned to STMicroelectronics S.r.l.
  • Patent number: 12638930
    Abstract: A method includes receiving electrostatic sensor data in a processor of an electronic device from an electrostatic sensor mounted behind a touchscreen of the electronic device and using the electrostatic sensor data to determine when the touchscreen is being used. Based on whether or not the touchscreen is being used, an on-table detection (OTD) algorithm is selected from a plurality of available OTD algorithms. In one or more examples, the OTD algorithm may also be selected based on the current device mode of the electronic device, which may be determined from a lid angle, a screen angle, and a keyboard angle of the electronic device. The selected OTD algorithm is run to determine whether or not the electronic device is located on a stationary or stable surface.
    Type: Grant
    Filed: November 12, 2024
    Date of Patent: May 26, 2026
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Stefano Paolo Rivolta, Federico Rizzardini
  • Publication number: 20260142650
    Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.
    Type: Application
    Filed: January 6, 2026
    Publication date: May 21, 2026
    Applicant: STMicroelectronics S.r.l.
    Inventors: Domenico TRIPODI, Luca GIUSSANI, Simone Ludwig DALLA STELLA
  • Patent number: 12635439
    Abstract: A process for manufacturing a silicon carbide semiconductor device includes providing a silicon carbide wafer, having a substrate. An epitaxial growth for formation of an epitaxial layer, having a top surface, is carried out on the substrate. Following upon the step of carrying out an epitaxial growth, the process includes the step of removing a surface portion of the epitaxial layer starting from the top surface so as to remove surface damages present at the top surface as a result of propagation of dislocations from the substrate during the previous epitaxial growth and so as to define a resulting top surface substantially free of defects.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: May 19, 2026
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nicolo′ Piluso, Andrea Severino, Stefania Rinaldi Beatrice, AngeloAnnibale Mazzeo, Leonardo Caudo, Alfio Russo, Giovanni Franco, Anna Bassi
  • Patent number: 12629039
    Abstract: An earphone device has a casing having a measurement portion dedicated to acquisition of at least one measurement quantity with the earphone device arranged outside an ear of a subject. The earphone device is provided with at least one sensor, operatively coupled to the measurement portion within the casing for acquiring signals indicative of the measurement quantity, and a processing module that processes the signals acquired by the sensor so as to provide a processed output signal for monitoring the measurement quantity, as a function of the acquired signals. Electrical-connection elements define electrical paths within the casing in electrical connection with the sensor.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: May 19, 2026
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enrico Rosario Alessi, Enri Duqi, Fabio Passaniti
  • Patent number: 12633343
    Abstract: A word line activation unit of an in-memory computation generates activation signals as a function of an input value. The in-memory computation device includes a memory array with a plurality of memory cells (each storing a computational weight) coupled to a bit line and each to a word line and a digital detector. A cell current flows through each memory cell as a function of the activation signal and the computational weight and a bit line current is generated as a function of a summation of the cell currents. The digital detector performs successive iterations on the bit line current. In each iteration: an integration stage generates an integration signal indicative of a time integral of the bit line current, and resets the integration signal when the integration signal reaches a threshold; and the counter stage updates the output signal in response to the integration signal reaching the threshold.
    Type: Grant
    Filed: December 18, 2023
    Date of Patent: May 19, 2026
    Assignee: STMicroelectronics S.r.l.
    Inventors: Riccardo Zurla, Marco Pasotti, Marcella Carissimi, Alessandro Cabrini
  • Patent number: 12625171
    Abstract: In accordance with an embodiment, a method of measuring a load current flowing through a current measurement resistor coupled between a source node and a load node includes: measuring a first voltage across a replica resistor when a first end of the replica resistor is coupled to the source node and a second end of the replica resistor is coupled to a reference current source; measuring a second voltage across the replica resistor when the second end of the replica resistor is coupled to the source node and the first end of the replica resistor is coupled to the reference current source; measure a third voltage across the current sensing resistor; and calculating a corrected current measurement of the load current based on the measured first voltage, the measured second voltage and the measured third voltage.
    Type: Grant
    Filed: October 24, 2023
    Date of Patent: May 12, 2026
    Assignee: STMicroelectronics S.r.l.
    Inventor: Paolo Angelini
  • Patent number: 12628699
    Abstract: Electronic device comprising at least a first and a second branch, each branch including a first and a second transistor arranged in series to each other and formed in respective dice of semiconductor material. The dice are sandwiched between a first substrate element and a second substrate element. The first and the second substrate elements are formed each by a multilayer including a first conductive layer, a second conductive layer and an insulating layer extending between the first and the second conductive layers. The first conductive layers of the first and the second substrate elements face towards the outside of the electronic device and define a first and a second main face of the electronic device. The second conductive layer of the first and the second substrate elements is shaped so as to form contact regions facing and in selective electrical contact with the plurality of dice.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: May 12, 2026
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca Stella, Agatino Minotti, Francesco Salamone
  • Patent number: 12627462
    Abstract: The present disclosure relates to a method including: the generation, by a computing device, of a first key and a bootstrapping key; the provision of the first key and an identifier of the bootstrapping key to an electronic device and the provision of the bootstrapping key and the identifier to a server; the fully homomorphic encryption, by the electronic device, of a first data value, stored in the electronic device, by using the first key; and the provision, by the electronic device, of the encrypted first data value and of the identifier, to the server.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: May 12, 2026
    Assignee: STMicroelectronics S.r.l.
    Inventors: Amedeo Veneroso, Vincenzo Pascariello, Alfonso Tramontano
  • Patent number: 12620998
    Abstract: A circuit includes at least one coupling node configured to be coupled, via a cable, to a load to transmit a supply voltage thereto. The circuit includes test circuitry configured to sense at least one sensing signal indicative of a value of the cable impedance and/or of the cable voltage across the cable, to perform a comparison between the at least one sensing signal and at least one threshold indicative either of a threshold resistance value for the cable impedance or indicative of a threshold voltage value for the cable voltage, produce a comparison signal as a result of the comparison.
    Type: Grant
    Filed: January 17, 2024
    Date of Patent: May 5, 2026
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Alberto Bianco, Francesco Ciappa, Donato Bondetti
  • Patent number: 12619678
    Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and mode control circuitry. In a first mode of operation, the mode control circuitry stores feature data in a feature line buffer and stores kernel data in a kernel buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. In a second mode of operation the mode control circuitry stores feature data in the kernel buffer and stores kernel data in the feature line buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: May 5, 2026
    Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Michele Rossi, Thomas Boesch, Giuseppe Desoli
  • Patent number: 12622040
    Abstract: The present disclosure is directed to a diode with a semiconductor body of silicon including a cathode region, which has a first conductivity type and is delimited by a front surface; and an anode region, which has a second conductivity type and extends into the cathode region from the front surface. The diode further includes a barrier region of cobalt disilicide, arranged on the anode region; and a metallization region of aluminum or of an aluminum alloy, arranged on the barrier region. The barrier region contacts the anode region.
    Type: Grant
    Filed: January 4, 2023
    Date of Patent: May 5, 2026
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Ettore Chiacchio, Ignazio Bertuglia
  • Patent number: 12619065
    Abstract: A process for manufacturing a microelectromechanical mirror device includes, in a semiconductor wafer, defining a support frame, a plate connected to the support frame so as to be orientable around at least one rotation axis, and cantilever structures extending from the support frame and coupled to the plate so that bending of the cantilever structures causes rotations of the plate around the at least one rotation axis. The process further includes forming piezoelectric actuators on the cantilever structures, forming pads on the support frame, and forming spacer structures protruding from the support frame more than both the pads and the stacks of layers forming the piezoelectric actuators.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: May 5, 2026
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Carminati, Nicolo' Boni, Irene Martini, Massimiliano Merli, Laura Oggioni
  • Patent number: 12622020
    Abstract: A MOSFET transistor device includes a functional layer of silicon carbide, having a first conductivity type. Gate structures are formed on a top surface of the functional layer and each includes a dielectric region and an electrode region. Body wells having a second conductivity type are formed within the functional layer, and the body wells are separated from one another by surface-separation regions. Source regions having the first conductivity type are formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified concentration of dopant as compared to the concentration of the functional layer.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: May 5, 2026
    Assignee: STMicroelectronics S.r.l.
    Inventors: Patrick Fiorenza, Fabrizio Roccaforte, Edoardo Zanetti, Mario Giuseppe Saggio
  • Patent number: 12613344
    Abstract: A method corrects an ionospheric error affecting pseudo-range measurements in a GNSS receiver receiving a plurality of satellite signals from a plurality of satellites of the constellation of satellites. The method is performed in a navigation processing procedure performed at a GNSS receiver, receiving pseudo-range measurements previously calculated by the GNSS receiver obtained from a first carrier signal and a second carrier signal in the satellite signals, in particular in GPS bands L1 and L5. The method includes performing a correction procedure of the pseudo-range measurements including applying to the pseudo-range measurements corrections for predictable errors obtaining corrected pseudo-ranges and applying to the corrected pseudo-range measurements a further ionospheric error correction calculation to obtain further ionospheric error correction values.
    Type: Grant
    Filed: October 4, 2023
    Date of Patent: April 28, 2026
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Michele Renna, Nicola Matteo Palella
  • Patent number: 12613828
    Abstract: An example processing system includes a processing circuit, a volatile memory and a CAN communication controller circuit. The CAN communication controller circuit includes configuration and status registers. A transmission handler circuit and a reception handler circuit transmits and receives data via the CAN core circuit by exchanging data with the volatile memory based on the configuration data stored to the configuration and status registers, and filter elements stored to the volatile memory. Specifically, the processing system further includes a hardware host circuit comprising a non-volatile memory configured to store first configuration data (CD1) and second configuration data (CD2). The CD1 includes configuration data to be transferred to the configuration and status registers of the CAN communication controller circuit and the CD2 includes at least one filter element to be transferred to the volatile memory. A control circuit manages an initialization mode, a reception mode and a transmission mode.
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: April 28, 2026
    Assignees: STMicroelectronics Application GMBH, STMicroelectronics S.r.l.
    Inventors: Mirko Dondini, Calogero Andrea Trecarichi, Fred Rennig
  • Patent number: 12613274
    Abstract: An assembly for detecting a structural defect in a semiconductor die is provided. The assembly includes a defect-detection sensor and a microcontroller. The defect-detection sensor includes a plurality of resistive paths of electrical-conductive material in the semiconductor die, each of which has a first end and a second end and extends proximate a perimeter of the semiconductor die. The defect-detection sensor includes a plurality of signal-generation structures, each coupled to a respective resistive path and configured to supply a test signal to the resistive path. The microcontroller is configured to control the signal-generation structures to generate the test signals, acquire the test signals in each resistive paths, test an electrical feature of the resistive paths by performing an analysis of the test signals acquired and detect the presence of the structural defect in the semiconductor die based on a result of the analysis of the test signals acquired.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: April 28, 2026
    Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Mauro Giacomini, Fabio Enrico Carlo Disegni, Rajesh Narwal, Pravesh Kumar Saini, Mayankkumar Hareshbhai Niranjani
  • Patent number: 12614967
    Abstract: A control device for a switching voltage regulator having a switching circuit receives a set of measurement signals including a first measurement signal indicative of an output voltage of the switching voltage regulator. A burst-mode controller is configured to monitor the output voltage with respect to a first threshold and a second threshold higher than the first threshold, and to provide, in response, a burst signal. A driving-signal generation stage is configured to provide at least one switching control signal for the switching circuit based on the burst signal and the set of measurement signals. The driving-signal generation stage has a feedback module configured to provide a control signal based on the burst signal and an error signal indicative of a difference between the first measurement signal and a reference signal.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: April 28, 2026
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ivan Floriani, Stefano Castorina, Giulia Altamura, Emanuele Moretti
  • Publication number: 20260113030
    Abstract: In an electronic device, a pulse generator receives an input signal and a clock signal and produces a transmission signal that includes a pulse following each edge of the input signal and of the clock signal. The pulse is low when the input signal is low and high when the input signal is high. A transmitter produces, at its two output nodes, a replica of the transmission signal and the complement of the transmission signal. A galvanic isolation barrier is coupled to the output nodes of the transmitter and produces a differential signal that includes a positive spike at each rising edge of the transmission signal and a negative spike at each falling edge of the transmission signal.
    Type: Application
    Filed: December 18, 2025
    Publication date: April 23, 2026
    Applicant: STMicroelectronics S.r.l.
    Inventors: Carlo CURINA, Valerio BENDOTTI
  • Publication number: 20260108945
    Abstract: The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200° C. and in some embodiments at about 150° C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.
    Type: Application
    Filed: December 19, 2025
    Publication date: April 23, 2026
    Applicant: STMicroelectronics S.r.l.
    Inventors: Cristina MANOLA, Rosa Lucia TORRISI, Simone RASCUNÁ, Gabriele BELLOCCHI, Annalinda CONTINO, Giuseppe MACCARONE
  • Patent number: 12608579
    Abstract: A dual interface laminated card having a stack of layers includes at least a first core plastic layer, a second core plastic layer disposed over the first core plastic layer, an antenna inlay disposed between the second core plastic layer and first core plastic layer, and a micromodule disposed over the second core plastic layer. The core plastic layers are recycled plastic layers comprising a major percentage, in particular at least 80%, of low surface energy plastic. The laminated card further comprises at least a first layer of polyurethane heat activatable glue, coupled to a side facing the antenna inlay of at least one of the first and second core plastic layers such that the antenna inlay and the at least one core plastic layer are bonded together.
    Type: Grant
    Filed: September 10, 2024
    Date of Patent: April 21, 2026
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Antonio Sismundo, Giuliano Filpi, Antonio Amoroso, Massimo Sena