Patents Assigned to STMicroelectronics SA.A.
  • LASER DEVICE AND PROCESS FOR FABRICATING SUCH A LASER DEVICE
    Publication number: 20180278021
    Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).
    Type: Application
    Filed: May 30, 2018
    Publication date: September 27, 2018
    Applicants: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Thomas Ferrotti, Badhise Ben Bakir, Alain Chantre, Sebastien Cremer, Helene Duprez
  • REFRACTORY CIRCUIT FOR INTEGRATED ARTIFICIAL NEURON DEVICE
    Publication number: 20180276536
    Abstract: An integrated artificial neuron device includes a refractory circuit configured to inhibit signal integration for an inhibition duration after delivery of an output signal. The refractory circuit includes a first MOS transistor coupled between an input node and a reference node and having a gate connected to the output node by a second MOS transistor having a first electrode coupled to the supply node and a gate coupled to the output node. The refractory circuit further includes a resistive-capacitive circuit coupled between the supply node, the reference node and the gate of the second MOS transistor. An inhibition duration depends on a time constant of the resistive-capacitive circuit.
    Type: Application
    Filed: September 7, 2017
    Publication date: September 27, 2018
    Applicant: STMicroelectronics SA
    Inventors: Philippe Galy, Thomas Bedecarrats
  • INTEGRATED ARTIFICIAL NEURON DEVICE
    Publication number: 20180276526
    Abstract: An integrated artificial neuron device includes an input signal node, an output signal node and a reference supply node. An integrator circuit receives and integrates an input signal to produce an integrated signal. A generator circuit receives the integrated signal and, when the integrated signal exceeds a threshold, delivers the output signal. The integrator circuit includes a main capacitor coupled between the input signal node and the reference supply node. The generator circuit includes a main MOS transistor coupled between the input signal node and the output signal node. The main MOS transistor has a gate that is coupled to the output signal node, and a substrate that is mutually coupled to the gate.
    Type: Application
    Filed: September 1, 2017
    Publication date: September 27, 2018
    Applicant: STMicroelectronics SA
    Inventors: Philippe Galy, Thomas Bedecarrats
  • Method for processing signals originating from one or more sensors, in particular proximity sensors, for the recognition of a movement of an object and corresponding device
    Patent number: 10072923
    Abstract: The method for processing signals originating for example from several proximity sensors for the recognition of a movement of an object, comprises first respective samplings of the said signals delivered by the sensors so as to obtain a first set of first date-stamped samples, the generation, from the first set of first date-stamped samples, of new sampling times comprising a start of movement time, an end of movement time, and times regularly spaced between the start of movement time and the end of movement time, a re-sampling of the signal delivered by each sensor between the start of movement time and the end of movement time at the said new sampling times using the first samples, in such a manner as to generate a second set of second date-stamped samples, and a processing of the said second set of date-stamped samples by a movement recognition algorithm.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: September 11, 2018
    Assignee: STMICROELECTRONICS SA
    Inventor: Stéphane Valente
  • Electronic device with an upscaling processor and associated methods
    Patent number: 10075702
    Abstract: An electronic device includes a single-photon avalanche diode (SPAD) array and readout circuitry coupled thereto. The readout circuitry generates a depth map having a first resolution, and a signal count map having a second resolution greater than the first resolution. The depth map corresponds to distance observations to an object. The signal count map corresponds to intensity observation sets of the object, with each intensity observation set including intensity observations corresponding to a respective distance observation in the depth map. An upscaling processor is coupled to the readout circuitry to calculate upscaling factors for each intensity observation set so that each distance observation has respective upscaling factors associated therewith. The depth map is then upscaled from the first resolution to the second resolution based on the respective upscaling factors.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: September 11, 2018
    Assignee: STMICROELECTRONICS SA
    Inventors: Olivier Pothier, Arnaud Bourge
  • COMPACT PROTECTION DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGE
    Publication number: 20180254270
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Application
    Filed: September 1, 2017
    Publication date: September 6, 2018
    Applicant: STMicroelectronics SA
    Inventor: Johan Bourgeat
  • Method of manufacturing a waveguide
    Patent number: 10067291
    Abstract: A method of manufacturing a waveguide in a glass plate is disclosed. The glass plate is scanned with a laser beam directed orthogonally to the glass plate to form a trench according to a pattern of the waveguide to be formed. The scanning is performed by pulses of the laser beam having a duration between 2 and 500 femtoseconds. The glass plate with the trench is treated with hydrofluoric acid. After treating the glass plate, the trench is filled with a material having an index different from that of glass, and, after filling the trench, a cladding layer is deposited.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: September 4, 2018
    Assignee: STMicroelectronics SA
    Inventors: Cédric Durand, Frédéric Gianesello, Folly Eli Ayi-Yovo
  • MACH-ZEHNDER (MZ) RING OPTICAL MODULATOR
    Publication number: 20180246389
    Abstract: A Mach-Zehnder ring modulator includes a first optical path having a first diode and a optical path having a second diode. Each of the first and second diodes operates responsive to a voltage signal by modifying a phase of a light signal. A first optical coupler provides first and second light signals to the first and second optical paths, respectively. A second optical coupler couples outputs from the first and second optical paths. A feedback path is coupled between an output of the second optical coupler and an input of the first optical coupler.
    Type: Application
    Filed: August 17, 2017
    Publication date: August 30, 2018
    Applicant: STMicroelectronics SA
    Inventors: Valerie Danelon, Denis Pache, Christophe Arricastres
  • SOI integrated circuit equipped with a device for protecting against electrostatic discharges
    Patent number: 10062681
    Abstract: A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: August 28, 2018
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA, Centre National de la Recherche Scientifique
    Inventors: Yohann Solaro, Sorin Cristoloveanu, Claire Fenouillet-Beranger, Pascal Fonteneau
  • Method and circuit for integrated circuit body biasing
    Patent number: 10050037
    Abstract: The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 14, 2018
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Florian Cacho, Vincent Huard
  • DEVICE FOR PROTECTION AGAINST ELECTROSTATIC DISCHARGES WITH A DISTRIBUTED TRIGGER CIRCUIT
    Publication number: 20180197848
    Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.
    Type: Application
    Filed: March 7, 2018
    Publication date: July 12, 2018
    Applicant: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Laser device and process for fabricating such a laser device
    Patent number: 10014660
    Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: July 3, 2018
    Assignees: Commisariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Thomas Ferrotti, Badhise Ben Bakir, Alain Chantre, Sebastien Cremer, Helene Duprez
  • Method of manufacturing a nanostructured spectral filter
    Patent number: 10014337
    Abstract: A spectral filter is manufactured using a process wherein a first rectangular bar is formed within a first layer made of a first material, said first rectangular bar being made of a second material having a different optical index. The process further includes, in a second layer over the first layer, a second rectangular bar made of the second material. The second rectangular bar is positioned in contact with the first rectangular bar. The second layer is also made of the first material.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 3, 2018
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Romain Girard Desprolet, Michel Marty, Salim Boutami, Sandrine Lhostis
  • Method for patterning a thin film
    Patent number: 10014183
    Abstract: A method for producing at least one pattern in a layer resting on a substrate, including: a) making amorphous at least one first block of an upper layer of crystalline material resting on a first amorphous supporting layer, while the crystalline structure of a second block of the upper layer that adjoins and is juxtaposed with the first block is preserved; b) partially recrystallizing the first block by using at least one side surface of the second block that is in contact with the first block as an area for the start of a recrystallization front, the partial recrystallization being carried out to preserve a region of amorphous material in the first block; c) selectively etching the amorphous material of the upper layer with respect to the crystalline material of the upper layer to form at least one first pattern in the upper layer.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: July 3, 2018
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS SA
    Inventors: Shay Reboh, Laurent Grenouillet, Yves Morand
  • METHOD FOR MANUFACTURE OF A SEMICONDUCTOR WAFER SUITABLE FOR THE MANUFACTURE OF AN SOI SUBSTRATE, AND SOI SUBSTRATE WAFER THUS OBTAINED
    Publication number: 20180166318
    Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.
    Type: Application
    Filed: February 9, 2018
    Publication date: June 14, 2018
    Applicant: STMicroelectronics SA
    Inventors: Didier Dutartre, Herve Jaouen
  • Electronic device provided with a thermal dissipation member
    Patent number: 9997431
    Abstract: An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support and a front face opposite its rear face. A block is provided for at least partially encapsulating the component above the front face of the support. The device also includes at least one thermal dissipation member having a flexible sheet having at least two portions folded onto one another while forming at least one fold between them, these portions facing one another at least partly.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: June 12, 2018
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Rafael Augusto Prieto Herrera, Jean-Philippe Colonna, Perceval Coudrain
  • Method of contactless communication between an object and a reader by active load modulation
    Patent number: 9998178
    Abstract: A method can be used for contactless communication of an object with a reader using active load modulation. A main clock signal is generated within the object. The generating includes a calibration phase and a transmission phase. The calibration phase includes locking an output signal of a controlled main oscillator onto a phase and frequency of a secondary clock signal received from the reader and estimating a frequency ratio between a frequency of the output signal of the main oscillator and a reference frequency of a reference signal originating from a reference oscillator. The transmission phase includes only frequency-locking the output signal of the main oscillator onto the frequency of the reference signal corrected by the estimated frequency ratio.
    Type: Grant
    Filed: February 19, 2017
    Date of Patent: June 12, 2018
    Assignee: STMicroelectronics SA
    Inventors: Sebastien Dedieu, Marc Houdebine
  • Device for protection against electrostatic discharges
    Patent number: 9997907
    Abstract: An electronic device includes first and second terminals with an electronic circuit coupled there between. The electronic circuit includes a protection circuit and a resistive-capacitive circuit. The resistive-capacitive circuit triggers the protection circuit to protect against electrostatic discharges in the presence of a current pulse between the first and second terminals. A control circuit is configured to slow down a discharge from the resistive-capacitive circuit when the protection circuit is triggered.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: June 12, 2018
    Assignee: STMicroelectronics SA
    Inventors: Johan Bourgeat, Boris Heitz, Jean Jimenez
  • Imaging device with filtering of the infrared radiation
    Patent number: 9998689
    Abstract: An imaging device includes at least one photosite formed in a semiconducting substrate and fitted with a filtering device for filtering at least one undesired radiation. The filtering device is buried in the semiconducting substrate at a depth depending on the wavelength of the undesired radiation.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: June 12, 2018
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS, STMicroelectronics SA
    Inventors: David Coulon, Benoit Deschamps, Frederic Barbier
  • Photodetector on silicon-on-insulator
    Patent number: 9997550
    Abstract: A photodetector is formed in a silicon-on-insulator (SOI) type semiconductor layer. The photodetector includes a first region and a second region of a first conductivity type separated from each other by a central region of a second conductivity type so as to define a phototransistor. A transverse surface of the semiconductor layer is configured to receive an illumination. The transverse surface extends orthogonally to an upper surface of the central region.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: June 12, 2018
    Assignee: STMICROELECTRONICS SA
    Inventor: Bruno Rauber