Patents Assigned to STMicroelectronics SA.A.
  • Patent number: 10432023
    Abstract: A contactless card is powered by an antenna connected to the input of a rectifier. An output of the rectifier is coupled to a processing unit that consumes a first current output from the rectifier. A current regulation circuit is connected to the output of the rectifier. The current regulation circuit operates to absorb a second current from the output of the rectifier such that a sum of the first and second currents is a constant current.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: October 1, 2019
    Assignee: STMicroelectronics SA
    Inventor: Julien Goulier
  • Patent number: 10429940
    Abstract: An electronic device includes at least one laser source configured to direct laser radiation toward a user's hand. Laser detectors are configured to receive reflected laser radiation from the user's hand. A controller is coupled to the at least one laser source and laser detectors and configured to determine a set of distance values to the user's hand for each respective laser detector and based upon a time-of-flight of the laser radiation. The controller also determines a hand gesture from among a plurality of possible hand gestures based upon the sets of distance values using Bayesian probabilities.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 1, 2019
    Assignee: STMicroelectronics SA
    Inventor: Olivier Pothier
  • Publication number: 20190285694
    Abstract: A method for determining a margin of use of an integrated circuit includes monitoring at least one sensor so as to determine at least one physical parameter representative of use of the integrated circuit, evaluating the at least one physical parameter to determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter, and calculating the margin of use for the integrated circuit from a comparison of the instantaneous state of aging with a presumed state of aging. If operation of the integrated circuit is outside the margin of use, at least one operating performance point of the integrated circuit is adjusted so as to bring operation of the integrated circuit back within the margin of use.
    Type: Application
    Filed: May 28, 2019
    Publication date: September 19, 2019
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Vincent HUARD, Chittoor PARTHASARATHY
  • Publication number: 20190288079
    Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 19, 2019
    Applicant: STMicroelectronics SA
    Inventors: Sotirios ATHANASIOU, Philippe GALY
  • Patent number: 10419434
    Abstract: A device protects an incoming multimedia signal with a protection that is controllable and configured for enabling or disabling an application for an interface protection on an outgoing signal coming from the incoming signal. An output interface is configured for delivering the outgoing signal on an output. An authorization process is performed for authorizing or otherwise a control over the enabling or disabling of the interface protection application depending on security rules.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronics SA
    Inventor: Jocelyn Leheup
  • Patent number: 10419432
    Abstract: An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: September 17, 2019
    Assignees: STMicroelectronics SA, STMicroelectronics (Grenoble2) SAS, STMicroelectronics S.R.L.
    Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Hajer Ferjani, Giuseppe Maruccia, Raffaele Guarrasi, Giuseppe Guarnaccia
  • Publication number: 20190267367
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Application
    Filed: May 8, 2019
    Publication date: August 29, 2019
    Applicant: STMicroelectronics SA
    Inventor: Johan BOURGEAT
  • Patent number: 10395013
    Abstract: A signal is protected against an attack by an enhancement process that checks the conformity of an actual state of the signal with respect to an expected state. A protective action is exercised on the signal if the actual state of the signal is not in conformity with the expected state, so as to neutralize or nullify said attack.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: August 27, 2019
    Assignee: STMicroelectronics SA
    Inventors: Jocelyn Leheup, Herve Sibert
  • Patent number: 10395383
    Abstract: A method estimates an ego-motion of an apparatus between a first image and a second image of a succession of images captured by the apparatus, in a SLAM type algorithm containing a localization part including the ego-motion estimating and a mapping part. The ego-motion comprises a 3D rotation of the apparatus and a position variation of the apparatus in the 3D space, and the ego-motion estimating comprises performing a first part and performing a second part after having performed the first part, the first part including estimating the 3D rotation of the apparatus and the second part including, the 3D rotation having been estimated, estimating the position variation of the apparatus in the 3D space.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: August 27, 2019
    Assignee: STMICROELECTRONICS SA
    Inventors: Manu Alibay, Stéphane Auberger, Bogdan-Florin Stanciulescu
  • Patent number: 10379619
    Abstract: A method for controlling an apparatus, includes steps of: determining distance measurements of an object in a first direction, using distance sensors defining between them a second direction different from the first direction, assessing a first inclination of the object in relation to a second direction based on the distance measurements, and determining a first command of the apparatus according to the inclination assessment.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: August 13, 2019
    Assignees: STMicroelectronics SA, STMicroelectronics (Grenoble 2) SAS
    Inventors: Marc Drader, Jérémie Teyssier, Olivier Pothier
  • Publication number: 20190245258
    Abstract: A 90° hybrid inductive-capacitive coupling stage includes two first stage terminals capable of forming two stage inputs or two stage outputs and two second stage terminals capable of respectively forming two stage outputs or two stage inputs. The coupling stage is advantageously modular having a first stage axis of symmetry and a second stage axis of symmetry orthogonal to each other with neighboring inductive metal tracks being overlaid in at least one crossing region to form both an inductive circuit and a capacitive circuit. The metal tracks are coupled to the first stage terminals and to the second stage terminals such that the two first stage terminals are situated on one side of the first stage axis of symmetry and the two second stage terminals are situated on the other side of the first stage axis of symmetry.
    Type: Application
    Filed: July 12, 2016
    Publication date: August 8, 2019
    Applicant: STMicroelectronics SA
    Inventors: Vincent KNOPIK, Boris MORET, Eric KERHERVE
  • Publication number: 20190244857
    Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 8, 2019
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Didier DUTARTRE, Jean-Pierre CARRERE, Jean-Luc HUGUENIN, Clement PRIBAT, Sarah KUSTER
  • Patent number: 10374069
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 6, 2019
    Assignee: STMicroelectronics SA
    Inventor: Pascal Chevalier
  • Patent number: 10361657
    Abstract: An integrated circuit includes at least two identical, synchronous and independent oscillator circuits that are coupled one to one in parallel with each other at homologous oscillating nodes of the respective oscillator circuits. The coupling in parallel is made using at least one coupling track that is configured so as to not introduce any phase shift or to introduce a very small phase shift.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: July 23, 2019
    Assignee: STMicroelectronics SA
    Inventor: Emmanuel Chataigner
  • Patent number: 10355649
    Abstract: A voltage or current generator has a configurable temperature coefficient and includes a first voltage generator that generates a first voltage having a first negative temperature coefficient. A second voltage generator generates a second voltage having a second negative temperature coefficient different to the first negative temperature coefficient. A circuit generates an output level based on the difference between the first voltage scaled by a first scale factor and the second voltage scaled by a second scale factor.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: July 16, 2019
    Assignee: STMicroelectronics SA
    Inventors: Jean-Pierre Blanc, Severin Trochut
  • Patent number: 10340265
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: July 2, 2019
    Assignee: STMicroelectronics SA
    Inventor: Johan Bourgeat
  • Patent number: 10334168
    Abstract: A method determines a movement of an apparatus between capturing first and second images. The method includes testing model hypotheses of the movement by for example a RANSAC algorithm, operating on a set of first points in the first image and assumed corresponding second points in the second image to deliver the best model hypothesis. The testing includes, for each first point, calculating a corresponding estimated point using the tested model hypothesis, determining the back-projection error between the estimated point and the second point in the second image, and comparing each back projection error with a threshold. The testing comprises for each first point, determining a correction term based on an estimation of the depth of the first point in the first image and an estimation of the movement between the first and second images, and determining the threshold associated with the first point by using said correction term.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 25, 2019
    Assignee: STMICROELECTRONICS SA
    Inventors: Manu Alibay, Stéphane Auberger
  • Publication number: 20190181131
    Abstract: An electronic device for providing ESD protection is formed by a MOS transistor. the MOS transistor includes a source region and a drain region that are separated from each other by a channel-forming region. A first gate is located over the channel forming region. The drain region includes an extension region. A second gate is located over the extension region. The first and second gates are electrically connected to each other.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 13, 2019
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Louise DE CONTI
  • Patent number: 10312240
    Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 4, 2019
    Assignee: STMICROELECTRONICS SA
    Inventors: Hassan El Dirani, Yohann Solaro, Pascal Fonteneau
  • Patent number: 10312431
    Abstract: A method of manufacturing bistable strips having different curvatures, each strip including a plurality of portion of layers of materials, wherein at least one specific layer portion is deposited by a plasma spraying method in conditions different for each of the strips.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: June 4, 2019
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Emilie Trioux, Pascal Ancey, Stephane Monfray, Thomas Skotnicki, Skandar Basrour, Paul Muralt