Patents Assigned to STMicroelectronics SA.A.
  • ELECTRONIC CIRCUIT WITH ELECTROSTATIC DISCHARGE PROTECTION
    Publication number: 20200006320
    Abstract: A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conduction terminal of a diode (such as cathode) or a transistor (such as a drain). A silicide layer is provided at the doped region. The silicide layer has an area that only partially covers an area of the upper surface of the doped region. The partial area coverage facilitates modulating the threshold voltage and/or leakage current of an integrated circuit device.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Applicant: STMicroelectronics SA
    Inventors: Thomas BEDECARRATS, Louise DE CONTI, Philippe GALY
  • Method for adjusting at least one operating point of at least one integrated circuit of a system on a chip, and corresponding system on a chip
    Patent number: 10514749
    Abstract: A system on a chip includes at least one integrated circuit that is configured to operate at least at one operating point. A monitoring circuit acquires at least the cumulative duration of activity of the at least one integrated circuit. An evaluation circuit establish at least one instantaneous state of aging of the at least one integrated circuit based on the at least one cumulative duration of activity. An adjustment circuit operates to change the at least one operating point on the basis of the at least one state of aging of the at least one integrated circuit.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: December 24, 2019
    Assignees: STMicroelectonics (Crolles 2) SAS, STMicroelectronics (Alps) SAS, STMicroelectronics SA
    Inventors: Vincent Huard, Silvia Brini, Chittoor Parthasarathy
  • Electronic device for ESD protection
    Patent number: 10515946
    Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 24, 2019
    Assignee: STMicroelectronics SA
    Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
  • SWITCHED-MODE POWER CONVERTER
    Publication number: 20190386567
    Abstract: A switched-mode power converter device includes an inductive element coupling a first node receiving an input voltage to a second node. A first transistor couples the second node to a third node generating an output voltage. A control circuit includes a first switch coupling the third node to a control terminal of the first transistor.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 19, 2019
    Applicant: STMicroelectronics SA
    Inventors: Francois AGUT, Severin TROCHUT
  • LOW-DROPOUT VOLTAGE REGULATION DEVICE
    Publication number: 20190384338
    Abstract: A low-dropout voltage regulation device includes a power stage having an output terminal coupled to a load circuit, the load circuit being operable in a plurality of operating modes. The load circuit is configured to receive a different respective output current when in each of the plurality of operating modes. An error amplifier has an output coupled to an input terminal of the power stage. A compensation circuit is coupled to the input terminal of the power stage and is operable in a plurality of selectable configurations that are respectively tailored to the plurality of operating modes. The plurality of selectable configurations are selectable in response to a control signal representative of a current operating mode of the load circuit.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 19, 2019
    Applicant: STMicroelectronics SA
    Inventors: Lionel VOGT, Eoin Padraig O HANNAIDH
  • Laser device and process for fabricating such a laser device
    Patent number: 10511147
    Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: December 17, 2019
    Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Thomas Ferrotti, Badhise Ben Bakir, Alain Chantre, Sebastien Cremer, Helene Duprez
  • Flip-flop with a metal programmable initialization logic state
    Patent number: 10505522
    Abstract: A standard cell layout for a flip-flop includes a flip-flop circuit and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the flip-flop. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the flip-flop circuit for configuration programming of the flip-flop as an initialization in reset device (assertion of an initialization signal causing the flip-flop data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the flip-flop circuit for configuration programming of the flip-flop as an initialization in set device (assertion of the initialization signal causing the flip-flop data output to be set).
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Engels, Alain Aurand, Etienne Maurin
  • INTEGRATED ELECTRONIC DEVICE SUITABLE FOR OPERATION IN VARIABLE-TEMPERATURE ENVIRONMENTS
    Publication number: 20190372568
    Abstract: An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 5, 2019
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Renan LETHIECQ
  • REMOTELY POWERED CONTACTLESS CARD
    Publication number: 20190372393
    Abstract: A contactless card is powered by an antenna connected to the input of a rectifier. An output of the rectifier is coupled to a processing unit that consumes a first current output from the rectifier. A current regulation circuit is connected to the output of the rectifier. The current regulation circuit operates to absorb a second current from the output of the rectifier such that a sum of the first and second currents is a constant current.
    Type: Application
    Filed: August 20, 2019
    Publication date: December 5, 2019
    Applicant: STMicroelectronics SA
    Inventor: Julien GOULIER
  • Method of manufacturing a waveguide
    Patent number: 10488594
    Abstract: A method of manufacturing an optical device is disclosed. The method includes forming a waveguide in a glass plate. The method further includes scanning the glass plate with a laser beam directed at an acute angle with respect to a first surface to form a mirror trench in the glass plate. Scanning the glass plate with the first laser beam includes pulses of the laser beam that have a duration between 2 and 500 femtoseconds. The method also includes filling the mirror trench with a reflective material and depositing a cladding layer over the waveguide and mirror trench.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: November 26, 2019
    Assignee: STMICROELECTRONICS SA
    Inventors: Cédric Durand, Frédéric Gianesello, Folly Eli Ayi-Yovo
  • Methods of fabricating integrated circuit devices with components on both sides of a semiconductor layer
    Patent number: 10488587
    Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: November 26, 2019
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Alain Chantre, Sébastien Cremer
  • Heat-transferring and electrically connecting device and electronic device
    Patent number: 10480833
    Abstract: A heat-transferring device is formed by a stack that includes at least one heat-conducting layer and at least one heat-absorbing layer. The at least one heat-conducting layer has at least one heat-collecting section placed facing a heat source and at least one heat-evacuating section placed facing a heat sink. The at least one heat-absorbing layer includes a phase-change material. One face of the at least one heat-absorbing layer is adjoined to at least one portion of at least one face of the heat-conducting layer.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: November 19, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Rafael Augusto Prieto Herrera, Jean-Philippe Colonna, Perceval Coudrain
  • Negative charge pump circuit
    Patent number: 10476383
    Abstract: The disclosure relates to a negative charge pump circuit including a first capacitor; a first selector switch; a second selector switch; and a control circuit designed to, in a first phase of operation, alternately control the first and second selector switches in a first configuration in which the first and second electrodes of the first capacitor are respectively linked to the first and second nodes and in a second configuration in which the first and second electrodes of the first capacitor are respectively linked to the second and third nodes. In a second phase of operation, the control circuit forces the first selector switch to link the first electrode of the first capacitor to the second node and control the second selector switch so as to alternately link the second electrode of the first capacitor to the second and to the third node.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: November 12, 2019
    Assignee: STMicroelectronics SA
    Inventor: Thierry Di Gilio
  • Communications device with receiver chain of reduced size
    Patent number: 10469124
    Abstract: A communications device includes a transmission chain coupled to an antenna a receiver chain coupled to the antenna. The receiver chain includes an amplifier device having an input coupled to the antenna. A controlled switching circuit is included in the amplifier device and is operable to selectively disconnect conduction terminals of an amplifying transistor from power supply terminals when the transmission chain is operating to pass a transmit signal to the antenna.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: November 5, 2019
    Assignee: STMicroelectronics SA
    Inventors: Laurent Chabert, Raphael Paulin
  • Method for increasing the saturation of an image, and corresponding device
    Patent number: 10455123
    Abstract: An image formed from pixels each having components defining a color is processed to implement an increase in the saturation of the image depending on a gain applied by a transfer function depending on the components of the color of each pixel. The gain of the transfer function is parameterized using at least one control parameter respectively dedicated to at least one type of reference image content. The value of the at least one control parameter is calculated depending on the actual content of the image by implementing calculations including determining colorimetric statistics of the pixels of the image and processing the statistics in accordance with at least one processing model respectively associated with the at least one type of reference image content.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: October 22, 2019
    Assignee: STMicroelectronics SA
    Inventor: Estelle Lesellier
  • LOW LEAKAGE MOSFET SUPPLY CLAMP FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION
    Publication number: 20190319453
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.
    Type: Application
    Filed: April 12, 2018
    Publication date: October 17, 2019
    Applicants: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan SITHANANDAM, Divya AGARWAL, Ghislain TROUSSIER, Jean JIMENEZ, Malathi KAR
  • INTEGRATED SILICON CONTROLLED RECTIFIER (SCR) AND A LOW LEAKAGE SCR SUPPLY CLAMP FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION
    Publication number: 20190319454
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated SCR device. The SCR device may include an embedded field effect transistor (FET) having an insulated gate that receives a trigger signal from an ESD detection circuit. The SCR device may alternatively include a variable substrate resistor having an insulated gate that receives a trigger signal from an ESD detection circuit.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 17, 2019
    Applicants: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan SITHANANDAM, Divya AGARWAL, Jean JIMENEZ, Malathi KAR
  • Transformer of the balanced-unbalanced type
    Patent number: 10447230
    Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 15, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Frédéric Gianesello, Romain Pilard, Cédric Durand
  • Method and apparatus for depth-map estimation of a scene
    Patent number: 10445892
    Abstract: The method of determination of a depth map of a scene comprises generation of a distance map of the scene obtained by time of flight measurements, acquisition of two images of the scene from two different viewpoints, and stereoscopic processing of the two images taking into account the distance map. The generation of the distance map includes generation of distance histograms acquisition zone by acquisition zone of the scene, and the stereoscopic processing includes, for each region of the depth map corresponding to an acquisition zone, elementary processing taking into account the corresponding histogram.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 15, 2019
    Assignee: STMICROELECTRONICS SA
    Inventors: Manu Alibay, Olivier Pothier, Victor Macela, Alain Bellon, Arnaud Bourge
  • Regulation of an RF amplifier
    Patent number: 10432154
    Abstract: A radiofrequency (RF) amplifier includes an input terminal, an output terminal, and a power supply and biasing stage having an output coupled to the input terminal. An amplification stage of the RF amplifier includes a first transistor having a control terminal coupled to the input terminal and a first conduction terminal coupled to the output terminal. The power supply and biasing stage is configured to generate a bias voltage at the control terminal of the first transistor to simultaneously regulate a power supply voltage of the amplification stage to a first voltage and a bias current of the amplification stage to a first current.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 1, 2019
    Assignee: STMicroelectronics SA
    Inventor: Lionel Vogt