Abstract: A method for manufacturing an electronic device includes forming, at a front side of a solid body of 4H-SiC having a first electrical conductivity, at least one implanted region having a second electrical conductivity opposite to the first electrical conductivity; forming, on the front side, a 3C-SiC layer; and forming, in the 3C-SiC layer, an ohmic contact region which extends through the entire thickness of the 3C-SiC layer, up to reaching the implanted region. A silicon layer may be present on the 3C-SiC layer; in this case, the ohmic contact also extends through the silicon layer.

Abstract: In an embodiment a method for managing a convolutional calculation carried out by a calculation unit adapted to calculate output data on output channels from convolution kernels applied to input data blocks on at least one input channel, wherein calculations on each input data block correspond respectively to an output datum on an output channel, and wherein the calculations with each convolution kernel correspond to the output data on each output channel respectively includes identifying a size of a memory location available in a temporary working memory of the calculation unit, pre-loading in the temporary working memory a maximum number of convolution kernels storable at the size of the memory; and controlling the calculation unit to calculate a set of output data calculable from pre-loaded convolution kernels.

Abstract: A circuit an amplifier stage that amplifier stage includes a positive amplifier branch and a negative amplifier branch and has current flow paths therethrough cascaded in a flow line for a core current for the amplifier stage between a supply node and a ground node. The positive and negative amplifier branches have respective input nodes configured to receive an input signal applied therebetween. A current mirror loop can be coupled to the respective input nodes of the positive and negative amplifier branches and provides an adjustable high-impedance bias source for the core current for the amplifier stage. In addition to, or instead of the current mirror loop, the circuit can include stability network having a gain bandwidth range. The amplifier stage is configured to short-circuit the output signal from the amplifier stage within the gain bandwidth range based on an output voltage setting signal.

Abstract: A semiconductor chip has a top metal layer with a passivation over an outer surface and including a first region and a second region. The passivation is fully removed from the first region and a contact layer for electrical wafer sorting probes is formed over the first region having the passivation fully removed therefrom. The passivation is initially only partly removed from the second region to protect the top met layer. Later, a remaining portion of the passivation is fully removed at the second region. Then, top metal layer at the second region provides a growth region for growing electrically conductive material over the second region.

Abstract: A power supply circuit includes a plurality of current supply circuits, each configured to provide an output current as a function of a respective digital control signal, and a measurement current proportional to the respective output current. A control circuit selects one of the measurement currents and one of the digital control signals associated with a current supply circuit. A comparison circuit generates a threshold current, and generates a comparison signal by comparing the selected measurement current with the threshold current. The control circuit sets, during a first phase, the threshold current to a first value smaller than an expected value for the selected measurement current as indicated by the selected digital control signal, and, during a second phase, to a second value greater than the expected value. The control circuit verifies whether the comparison signal is de-asserted during the first phase and asserted during the second phase.

Abstract: The present disclosure is directed to an electronic device including a semiconductor body having a first electrical conductivity and provided with a front side; an active area of the semiconductor body, accommodating the source and gate regions of the electronic device and configured to accommodate, in use, a conductive channel of the electronic device; and an edge region of the electronic device, surrounding the active area. The edge region accommodates at least in part: i) an edge termination region, having a second electrical conductivity opposite to the first electrical conductivity, extending into the semiconductor body at the front side; and ii) a gate connection terminal of conductive material, electrically coupled to the gate region, extending on the front side partially superimposed on the edge termination region and capacitively coupled with a portion of the semiconductor body adjacent and external to the edge termination region.

Abstract: MEMS ultrasonic transducer, MUT, device, comprising a semiconductor body with a first and a second main surface and including: a first chamber extending into the semiconductor body at a distance from the first main surface; a membrane formed by the semiconductor body between the first main surface and the first chamber; a piezoelectric element on the membrane; a second chamber extending into the semiconductor body between the first chamber and the second main surface; a central fluidic passage extending into the semiconductor body from the second main surface to the first chamber and traversing the second chamber; and one or more lateral fluidic passages extending into the semiconductor body from the second main surface to the second chamber. The one or more lateral fluidic passages, the central fluidic passage and the second chamber define a fluidic recirculation path that fluidically connects the first chamber with the outside of the semiconductor body.

Abstract: A sample treatment and molecule analysis cartridge is configured to be mounted in a treatment machine vertically. The cartridge has a sample inlet opening, a fluidic inlet, and a fluidic outlet. The cartridge houses an extraction chamber extending vertically from the sample inlet opening and connected to the fluidic inlet; a waste chamber extending vertically, alongside the extraction chamber; and a collector extending along the extraction chamber and the waste chamber and having a smaller height than the extraction chamber and the waste chamber. A fluidic circuit connects together the extraction chamber, the waste chamber, the collector, the fluidic inlet, and the fluidic outlet, and is configured to connect the fluidic outlet to vent openings of the extraction chamber, the waste chamber, and the collector, and to connect the bottom end of the extraction chamber to the fluidic inlet, the waste chamber, and the collector.

Abstract: The integrated sensor has a clock which provides a clock signal having a clock frequency; a digital detector which detects a power grid signal and generates a reference digital signal indicative of the power grid signal and having a sample rate which is a function of the clock frequency; and a timing monitoring stage which receives the reference digital signal and a nominal signal indicative of a nominal timing of the reference digital signal. The timing monitoring stage also compares the reference digital signal with the nominal signal and, in response, provides an error signal indicative of a timing error between the reference digital signal and the nominal signal.

Abstract: A radiofrequency detector comprises a squarer circuit comprising first and second branches coupled between a voltage supply and ground, the first branch comprising at least a first squarer transistor receiving a RF sinusoidal input voltage, the first squarer transistor being coupled to the voltage supply through a respective load, the second branch comprising a second reference transistor being coupled to the voltage supply through a respective load, an output voltage being formed at an output node of the first branch and a reference voltage being formed at a respective output node coupled to the load of the second branch, a squared voltage being obtained by a difference voltage of the output voltage and reference voltage, wherein the circuit is configured to feed back to a control electrode of the second reference transistor a feedback signal that is a function of the difference voltage.

Abstract: In an embodiment a processing system includes a sub-circuit including a three-state driver circuit, wherein the three-state driver circuit has a combinational logic circuit configured to monitor logic levels of a first signal and a second signal, and selectively activate one of the following switching states as a function of the logic levels of the first signal and the second signal: in a first switching state, connect the transmission terminal to the positive supply terminal by closing the first electronic switch, in a second switching state, connect the transmission terminal to the negative supply terminal by closing the second electronic switch, and in a third switching state, put the transmission terminal in a high-impedance state by opening the first electronic switch and the second electronic switch.

Abstract: Semiconductor chips to be singulated to individual semiconductor devices are arranged onto respective adjacent areas of a mounting substrate such as a pre-molded leadframe. The mounting substrate is made of a laminar, electrically conductive sculptured structure with molded electrically insulating material. Electrically conductive side formations in the adjacent areas of the mounting substrate include first and second pads at front and back surfaces, respectively, of the mounting substrate. The first contact pads at the front surface of the substrate include narrowed portions having side recesses. The second contact pads at the back surface of the substrate include widened portions having side extensions adjacent the side recesses. The electrically insulating material extends into the side recesses to provide anchoring formations of the insulating material to the electrically conductive sculptured structure of the mounting substrate.

Abstract: A low-drop out voltage regulator includes a pass element arranged between an input terminal and an output terminal, a feedback network configured to produce a feedback voltage derived from an output voltage, and an error amplifier configured to drive the pass element as a function of a difference between the feedback voltage and a reference voltage. An output transistor coupled in series with the pass element is controlled by a mode selection circuit. In response to assertion of a mode selection signal, the mode selection circuit turns on the output transistor to sink a current with a controlled magnitude from the output node. In response to de-assertion of the mode selection signal, the mode selection circuit sinks a current with a controlled magnitude from a control terminal of the output transistor to turn off the output transistor at a controlled rate.

Abstract: A device includes one or more inertial sensors and fusion circuitry coupled to the one or more inertial sensors. The inertial sensors, in operation, generate inertial sensor data with respect to a plurality of axes of movement. The fusion circuitry, in a polar fusion mode of operation, applies a plurality of polar rotation operations to the generated inertial sensor data to rotate the generated inertial sensor data onto an axis of the plurality of axes of movement. A fused data signal is generated based on a result of the plurality of polar rotation operations. The plurality of inertial sensors may include bone-conduction sensors.

Abstract: A circuit includes an amplifier and a feedback network coupled between the input and the output of the amplifier. The feedback network includes a plurality of parallel coupled branches, each branch having a first selection switch coupled to the input, a second selection switch coupled to the output, and an impedance between the first and second selection switches. Each branch includes a plurality of signal feedback paths coupled in parallel, each having a tuning switch coupled between the first selection switch and the second selection switch of that branch. A control unit is coupled to the feedback network and configured to vary a gain of the amplifier by selectively placing the first and second selection switches of each branch in a conductive state or a non-conductive state and selectively activating respective tuning switches of any branch having first and second selection switches in the conductive state.

Abstract: A LIDAR optical unit includes a photonic-integrated-circuit (PIC) affixed to a carrier. The PIC includes an input coupler and an array of output couplers, with a switchable optical network connecting the input coupler to different selected ones of the array of output couplers. A laser source is mounted to the PIC adjacent the input coupler such that laser light generated by the laser source is injected into the input coupler. An optical stack is mounted to the PIC adjacent the array of output couplers to receive laser light extracted from the switchable optical network by the array of output couplers. The optical stack includes an array of microlenses positioned so that a bottom surface thereof is mounted to the PIC, and an array of microprisms is stacked on the array of microlenses so that a bottom surface thereof is mounted to a top surface of the array of microlenses.

Abstract: Semiconductor chips are arranged on an elongated substrate and encapsulated by an insulating encapsulation. Electrically conductive formations and electrically conductive plating lines are plated on the insulating encapsulation using, for example, Laser Direct Structuring (LDS) or Direct Copper Interconnect (DCI) material. The electrically conductive plating lines include first transverse plating lines as well as second plating lines branching out from the first plating lines towards the electrically conductive formations. A first partial cutting step is then performed to form grooves which remove the first plating lines. An insulating material is dispensed in the grooves to encapsulate the end portions of the second plating lines. A second cutting step median along the groove and through the elongate substrate is performed to produce singulated semiconductor devices (such as “die pad up” Quad-Flat No-lead (QFN) packages). End portions of the second plating lines are encapsulated by the insulating material.

Abstract: A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.

Abstract: A random access memory (RAM) includes an array of arranged in rows and columns. The rows of the storage elements correspond to respective memory locations of the RAM. The storage elements of a row have a common gated-clock input and respective data inputs, and each row of the array of storage elements includes a plurality of D type latches. In operation, an address input of the RAM receives a memory address identifying a memory location in the RAM. Clock gating circuitry of the RAM, generates respective gated-clock signals for the rows of the array of storage elements based on the memory address received at the address input. Memory operation are performed using storage elements of the array based on the gated-clock signals.

Abstract: A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.