Abstract: A special rail is provided along each edge of an integrated circuit chip with bias circuits connected to the ends of each special rail. The bias circuits charge the special rail to the V.sub.DD voltage level during normal operation, and clamp the special rail to the V.sub.SS rail upon the occurrence of an overvoltage event. Input bonding pads are provided along each edge of the chip and are connected through diodes to the special rail so that 5 volt signals applied to the input bonding pads do not cause damage to the device when operated from a 3.3 volt supply. A signal line of extended length is provided between each input bonding pad and its receiver circuit and includes folded portions for adding to the length of the signal line to form a high frequency inductor to protect the receiver circuit at the onset of an overvoltage event before clamping becomes effective.

Abstract: A DC-to-DC converter includes an error amplifier; a ramp generator for generating a ramp signal at the first input of the error amplifier independent of the output of the error amplifier and so that the output of the error amplifier ramps up at a relatively slow rate to avoid overshoot of the desired output voltage of the converter during the start-up phase of the converter; and a ramp disable circuit for disabling the ramp signal upon reaching a value corresponding to the normal operating phase of the converter. The DC-to-DC converter preferably includes at least one power switch and pulse width modulation (PWM) control circuit cooperating with the power switch to provide a desired output voltage of the converter. The ramp generator in one embodiment comprises a current source and an external capacitor connected thereto. In yet another embodiment, the ramp generator may be provided by a staircase ramp generator comprising an amplifier and an integrating capacitor connected thereto.

Abstract: A sensor of instantaneous power which is dissipated through a power transistor of the MOS type connected between the output terminal of a power stage and ground. It comprises a MOS transistor having its gate terminal connected to that of the power transistor, source terminal connected to ground, and drain terminal connected to a circuit node which is coupled to the output terminal by means of a current mirror circuit which includes a resistive element in its input leg. Connected to the circuit node is the base terminal of a bipolar transistor which is respectively connected, through a diode and a constant current generator between the output terminal and ground.

Abstract: An electric muting circuit for soft muting of an audio signal is shown. It comprises a digitally controllable attenuation circuit having an audio signal input, an audio signal output and a control signal input and also comprises an up/down counter having a clock pulse input fed with clock pulses to be counted, a counting control input fed with a counting control signal controlling counting start and counting stop, and a count signal output from which a digital count signal is available and which a digital count signal input of the attenuation circuit.

Abstract: An electric circuit comprising at least one MOS switching transistor disposed on the side of high potential and a switchable charge pump supporting the switching-on phase of the MOS switching transistor at a pumping voltage output thereof with a pumping voltage higher than the potential of the supply voltage on the side of high potential at a pumping voltage output thereof. A control gate of the MOS switching transistor is connectable by means of a controllable switch to a high-potential-side supply voltage terminal or to the pumping voltage output depending on whether a predetermined threshold value on the switching-on ascending edge of the MOS switching transistor signal is exceeded or not.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a doped polysilicon layer disposed in the first opening and over a portion of the first dielectric layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A second dielectric layer having an opening therethrough is formed over the landing pad having an opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.

Abstract: A BiCMOS transconductor differential stage for high frequency filters includes an input circuit portion having signal inputs and a pair of MOS transistors having their respective gate terminals corresponding to the signal inputs. The differential stage has an output circuit portion having signal outputs and a pair of bipolar transistors connected together with a common base inserted between the inputs and the outputs in a cascode configuration. The differential stage includes a switching device associated with at least one of the bipolar transistors to change the connections between parasitic capacitors present in the differential stage. The switching device also has at least one added bipolar transistor connected in a removable manner in parallel with the corresponding bipolar cascode transistor.

Abstract: The present invention relates to a power amplifier having an output stage in MOS technology, including an upper half-output stage comprised of two P-channel MOS power transistors mounted as a current mirror, a lower half-output stage comprised of two N-channel MOS power transistors mounted as a current mirror, an output terminal of the amplifier corresponding to the common drains of a first MOS transistor of the upper stage and of a first MOS transistor of the lower stage, and a control stage in bipolar technology for setting, according to a control voltage, two control currents of the half-output stages.

Abstract: The invention relates to a method for detecting a threshold-crossing of a back electromotive force (bemf) measured in one phase of a multiple-phase motor, the one phase being set at a high impedance while at least one other phase is supplied by pulse-width modulation signal. The method includes the step of comparing the bemf with a threshold. The method includes, prior to the step of comparing, the steps of sampling the bemf during on-periods of the pulse-width modulation signal, and holding the bemf during off-periods of the pulse-width modulation signal.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.

Abstract: The present invention relates to an analog voltage-signal selector device of the type comprising at least one plurality of comparator circuits operating in parallel and each having at least a first and second input terminals and designed to receive respectively an analog voltage-comparison signal and analog voltage signals of predetermined value and at least one output terminal for digital voltage signals. This selector device also comprises at least one logic circuit having a plurality of input terminals each connected to a corresponding output terminal of the comparator circuits and at least one output terminal. Finally the selector incorporates at least one plurality of latches each having at least one input terminal connected to the output terminal of a corresponding comparator circuit and at least one drive terminal coupled to the output terminal of the logic circuit with each of the memory circuits having at least one output terminal corresponding to an output of the selector.

Abstract: A device for protection against electrostatic discharges on the terminals of a MOS integrated circuit and characterized in that it consists of a first and a second circuit branch coupled between the terminal to be protected and ground. The first circuit branch has two field transistors. The gate of the first field-effect transistor is connected to terminal to be protected, and the gate of the second field-effect transistor is connected to a first resistance of the second circuit branch. The second circuit branch has a third field-effect transistor with its gate terminal connected to ground and a second resistance inserted between the third transistor and the terminal to be protected.

Abstract: An integrated circuit wherein a planarization step has been performed before the primary metal deposition step, but after deposition of the adhesion and barrier layers. Thus the adhesion and barrier layers are present on the sidewalls of contact holes, but do not underlie the whole extent of the primary metallization.

Abstract: The memory device has a plurality of local boost circuits, each connected to a sector of the memory array, and each having a control circuit, at least a respective boost capacitor, and a respective drive circuit. Each drive circuit is only enabled in read mode, on receiving an address-transition-detect signal and a sector enabling signal, for reading memory cells forming part of the respective sector. The boost voltage is only supplied to the final inverter of the row decoder. A clamping diode limits the boost voltage to prevent undesired direct biasing of the PMOS transistors of the final inverters connected to the nonaddressed word lines. And the overvoltage is therefore only supplied locally when and where necessary.

Abstract: A programmable reference voltage source includes a nonvolatile memory cell, the floating-gate region of which stores electric charges determining a memorized threshold value. The drain terminal of the cell is biased at a constant voltage, and the source terminal is coupled to a constant-current source and to the inverting input of an operational amplifier having the noninverting input coupled to a reference voltage and the output coupled to the gate terminal of the cell. By defining the threshold of the cell as the gate voltage (measured with respect to ground) capable of causing the cell to be flown by the current set by the current source, the output voltage of the operational amplifier equals the threshold and may be used as a programmable reference in analog memories.

Abstract: A circuit for producing multiple pulse width modulated outputs. The circuit includes a logic device for each pulse width modulated output. Each of the logic devices includes a first input, a second input, and a clock input, and each of logic device produces a logical high output in response to a logical high at its first input in coincidence with a clock signal at its clock input. The logical high output of the logic device remains high until a logical high is applied at its second input in coincidence with a clock signal at the clock input, whereupon the logic device produces a logical low output. The logical low output of the logic device remains low until a logical high is again applied at its first input in coincidence with a clock signal at the clock input. The circuit includes programmable circuitry for selectively applying logical high and low signals to the first and second inputs of the logic devices.

Abstract: An integrated circuit device such as an SRAM operating in a battery backup mode, or operating in a quiescent mode when deselected in the operation of a portable electronic device, includes a power dissipation control circuit that reduces the voltage on an internal power supply node so that the memory array is powered at a minimum level sufficient to retain the data stored therein intact.

Abstract: Parallel testing of integrated circuit devices are facilitated such that it is not necessary that integrated circuit devices to be parallel tested be "ends only" devices. A side pad located along the sides, rather than the ends, of the integrated circuit device is electrically connected by multiplexing circuitry to a corresponding configurable probe pad located along the ends of the device. During parallel testing of the device, the side pad is effectively tested when the configurable probe pad is probed and tested. While the configurable probe pad is tested during parallel testing, the side pad is not directly exercised. Following parallel testing, the side pad is bonded to the device package but the configurable probe pad is not bonded to the device package.

Abstract: Parallel testing of integrated circuit devices are facilitated such that it is not necessary that integrated circuit devices to be parallel tested be "ends only" devices. A side pad located along the sides, rather than the ends, of the integrated circuit device is electrically connected by multiplexing circuitry to a corresponding configurable probe pad located along the ends of the device. During parallel testing of the device, the side pad is effectively tested when the configurable probe pad is probed and tested. While the configurable probe pad is tested during parallel testing, the side pad is not directly exercised. Following parallel testing, the side pad is bonded to the device package but the configurable probe pad is not bonded to the device package.

Abstract: A direct current boost converter which has a simple structure using only one coil, and which can apply a driving voltage to a capacitive load which reciprocates in polarity is discussed. A first direct current branch circuit composed of first and second transistors is connected in parallel to a second direct current branch circuit composed of the third and fourth transistors. A coil is connected between the intermediate nodes of the transistors of these direct current branch circuits, and these nodes are further connected to both terminals of an EL panel through first and second diodes. The nodes between the first and second diodes and the EL panel are grounded through fifth and sixth transistors, respectively. A clock signal is applied to the first and third transistors, and a gate signal with an opposing phase is applied to the second and fourth transistors.