Abstract: A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of field oxide regions are formed overlying a substrate electrically isolating a plurality of transistors encapsulated in a dielectric. LDD regions are formed in the substrate adjacent the transistors and the field oxide regions. Doped polysilicon raised source and drain regions are formed overlying the LDD regions and a tapered portion of the field oxide region and adjacent the transistor. These polysilicon raised source and drain regions will help to prevent any undesired amount of the substrate silicon from being consumed, reducing the possibility of junction leakage and punchthrough as well as providing a more planar surface for subsequent processing steps.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a doped polysilicon layer disposed in the first opening and over a portion of the first dielectric layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A second dielectric layer having an opening therethrough is formed over the landing pad having an opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.

Abstract: A current limiting circuit used with voltage regulators or other similar circuits is disclosed. The current limiting circuit uses two transistors, configured as a differential pair, combined with a fixed current source to limit the current available to a pass transistor of the voltage regulator.

Abstract: A filter circuit adjustably decreases or increases the amplitude of audio signals in a predetermined frequency range. The filter circuit includes a filter module having an RC network with at least one frequency-response-determining RC member whose resistor component R is realized in SC technology. A setting device is connected to the filter module such that its setting determines the frequency response of the SC filter. The setting device renders possible a neutral setting in which the effective audio signal path of the filter circuit circumvents the filter module so that no decrease or increase of the amplitude of individual frequency portions takes place. Furthermore, an audio signal processor comprises at least one audio signal input, at least one audio signal output, and at least one control input.

Abstract: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type disposed on a surface thereof and a dielectric layer including silicon nitride disposed on the surface. The dielectric layer includes openings at least partially disposed on the p-wells. The dielectric layer also includes a top layer comprising silicon dioxide having a thickness of less than ten angstroms. Trenches having a depth comparable to or greater than a depth of the wells extend into the substrate surface within the openings. A nonconductive material is disposed within the trenches and has an upper surface that is substantially coplanar with the dielectric layer. Portions of the dielectric layer are used as gate dielectrics for transistors.

Abstract: A DVD player that integrates a DVD device into a personal computer is provided. As such, the personal computer is able to output audio-visual works from a DVD CD-ROM. When integrating a DVD device with a personal computer, various problems must be overcome. For example, in a personal computer, the video display is controlled by a graphics controller, and in order to render an audio-visual stream in a personal computer, the audio-visual stream and the graphics controller must be synchronized. The synchronization problem arises because the graphics controller only displays data at the beginning of 33.4 millisecond time intervals. Thus, although the audio portion may be played almost immediately, the video portion may have to wait for up to 33.4 milliseconds before being displayed. In this manner, the audio portion and the video portion become unsynchronized which means that the audio portion plays before the corresponding video portion is displayed.

Abstract: A method for forming a plastic package for a power semiconductor electronic device to be encapsulated within a plastic case and to be coupled thermally to a heat sink element having a major surface exposed and at least one peripheral portion extending outwards from at least one side of the plastic case. The method forms the plastic case of the package by molding inside a main cavity of a mold after positioning a heat sink element in a suitable housing provided in a lower portion of the mold which opens into the main cavity of the mold. The method forms the heat sink element such that at least side surfaces jutting out of said side of the plastic case are, at least in a zone adjacent to that side and in the peripheral portion, inclined to form an angle .alpha. substantially greater than zero with a normal line to the major surface, so as to have a negative slope from outside.

Abstract: A method and structure for wave-shaping of digital waveforms of integrated circuit processes that do not have area efficient dielectric capacitors is disclosed. The dielectric capacitors of the prior art are replaced with a first, linearizing diode and a second diode of a wave-shaping circuit, each diode having a junction capacitance that varies with voltage applied across the diode. The first, linearizing diode is supplied with a constant current from a constant current source. A current inversely proportional to the junction capacitance of the first, linearizing diode is produced at a node defined as the connection between the constant current source and the first linearizing diode. The current at the node is supplied to the second diode to produce an output voltage of the wave-shaping circuit that is linear with respect to time.

Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs for digital signals, and an output for an analog signal. It also contains a charge integration circuit having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors corresponding to the plurality of converter inputs, the MOS transistors all having their source and drain terminals coupled together and to the input of the integration circuit, and having control terminals coupleable, under control from the plurality of inputs of digital signals, to different reference voltages having selected fixed values.

Abstract: The circuit is for translating a switching signal disposed between ground level and Vdd to a translated switching signal disposed between first and second voltages Vhsrc and Vhstrap. The circuit includes a bistable circuit formed by two branches which include two nMOS transistors the sources of which are connected to ground and are controlled, respectively, by a switching-on signal and by a switching-off signal derived from the switching signal by means of a buffer and an inverter, respectively. Two pMOS transistors having their sources at the voltage Vhstrap and the drain of one connected to the gate of the other output the translated switching signal at one of their drains. Two further pMOS transistors having gates at the first voltage Vhsrc are interposed between the two nMOS transistors and the two pMOS transistors.

Abstract: A circuit for clamping the voltage appearing on the bit lines of a dynamic random access memory (DRAM) device so that the voltage thereon is maintained above the low reference voltage source. The circuit includes pull-up devices connected to the bit lines of the DRAM device. The pull-up devices are active only when pull-down devices connected to the bit lines pull some of the bit lines towards the low reference voltage level.

Abstract: An integrated circuit package had leadless solderballs attached to the substrate with a conductive thermoplastic adhesive. The leadless solderballs are preferably made with a copper-nickel-gold alloy. The conductive thermoplastic is preferably of the silver fill type. The integrated circuit package is placed in a frame and held to the printed circuit board with a clamp or with a screw.

Abstract: A memory array is divided, at the design stage, into a plurality of elementary sectors; depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors of desired size and number; a correlating unit memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address is supplied to the correlating unit which provides for addressing the elementary sectors associated with the addressed composite sector on the basis of the memorized correlation table.

Abstract: An integrated circuit capacitor ladder which uses a differential pair of capacitors for each step in the ladder. By pairing a square with a rectangle of equal perimeter, the contributions of edge and corner elements can be canceled out. This adds area and complexity, but greatly increases the precision of scaling.

Abstract: A nonvolatile memory having a memory array including a plurality of data cells and a read circuit. The read circuit includes a plurality of sense amplifiers, each connected to a respective array branch to be connected to the data cells. The nonvolatile memory also includes a reference generating circuit including a single reference cell arranged outside the memory array and generates a reference signal. The reference generating circuit includes a plurality of reference branches, each connected to a respective sense amplifier, and circuits interposed between the reference cell and the reference branches to supply the reference branches with a signal based on the reference signal.

Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors having source and drain terminals which are coupled together and to an injection node, and at least one corresponding pair of generators of substantially step-like voltage signals having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors. The signal generators are such that the initial value of a first of the signals is substantially the equal of the final value of a second of the signals, and that the final value of the first signal is substantially the equal of the initial value of the second signal.

Abstract: A voltage regulator with load pole stabilization is disclosed. An error amplifier has a non-inverting input receiving a reference voltage and an inverting input receiving a feedback voltage from the output of the voltage regulator. A gain stage has an input connected to the output of the error amplifier and an output connected to a pass transistor that provides current to a load. A variable impedance device such as a FET transistor configured as a variable resistor is connected between the input and output of the gain stage to provide variable zero to cancel the varying pole when the output current drawn by the load fluctuates. Consequently, the disclosed voltage regulator has high stability without a significant increase in power dissipation.

Abstract: A memory structure features a write driver circuit that is controlled to assist equilibrate devices recover one or more bitlines attached to a memory cell following the completion of a write operation of the memory cell. After the write operation, a write bus true and a write bus complement generated by the write driver are coupled to bitlines and equilibration devices by passgates controlled by a control signal.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.

Abstract: The device comprises a first chain of scanning cells located at the stimulation input of each respective functional block of the integrated circuit and a second chain of scanning cells located at the assessment output of each respective functional block of the integrated circuit. Each cell comprises a master part, a slave part and switching circuit to alternately enable the master and slave parts under the control of respective master clock and slave clock signals coincident with opposite phases of a scanning clock signal having a substantially square wave. With each pair of chains of scanning cells there are associated clock generators to locally obtain the master and slave clocks from the scanning clock.