Abstract: The invention relates to a multi-level storage device including: at least a first plurality of cells storing an identical first number (greater than one) of binary data, and at least a corresponding for second plurality of cells for storing a second number of error check and correcting words equal to said first number, said words being respectively associated with sets of binary data, each including at least one binary data for each cell in said first plurality. In this way, many of the known error correction algorithms can be applied to obtain comparable results to those provided by binary memories. In addition, where multi-level cells are used for storing the error check and correcting words, the device dimension requirements can also be comparable.

Abstract: A semiconductor circuit includes a semiconductor layer having a surface and a monolithic output stage formed in the semiconductor layer. The monolithic output stage extends to the surface of the semiconductor layer and has a periphery within the semiconductor layer, an output terminal, and a supply terminal. A barrier well is formed in the semiconductor layer and adjacent to at least a portion of the periphery of the monolithic output stage. The barrier well extends to the surface of the semiconductor layer and has a first conductivity. A diode having first and second diode regions is disposed in the semiconductor layer. The first diode region is coupled to the supply terminal. The diode is operable to prevent current flow from the barrier well to the supply terminal when the voltage between the supply and output terminals has a first polarity.

Abstract: Driver and overload protection circuit for an electrical switch means. Switching control pulses with a minimum edge duration are fed to a two stage comparator circuit having first, lower and second, higher comparator threshold values. When the lower comparator threshold value is exceeded by a switching control pulse, the electrical switch means is rendered conducting. There is provided an overload detection circuit which, upon detection of overload of the electrical switch means, effects switching off of the same. For avoiding that turning on spikes upon each turning on of the electrical switch means, for example when switching capacitive loads, lead to deactivation of the switch means, any overload signal of the overload detector means is blocked as long as the instantaneous voltage value of the particular switching control pulse is not above the upper comparator threshold.

Abstract: In a high current, high frequency integrated circuit chip characteristic of producing an excess of internal on-chip circuit induced noise with respect to a low current, low frequency circuit implemented on the high current, high frequency integrated circuit chip, a method is disclosed for reducing noise in the low current, low frequency circuit. The method includes placing noise sensitive components of the low current, low frequency circuit external to the integrated circuit chip, corresponding to an off-chip placement. An exclusive power supply reference line V.sub.(REF) tapped off of a power supply bus internal to the integrated circuit chip is provided. The exclusive power supply reference line V.sub.(REF) is tapped off the internal power supply bus on-chip at a physical location proximate the low current, low frequency circuit and routed off-chip. The noise sensitive components are connected between the low current, low frequency circuit and the power supply reference line V.sub.

Abstract: A method of forming a portion of a semiconductor integrated circuit having a semiconductor substrate as well as the resulting integrated circuit. In the inventive method, various steps are involved. In one embodiment, for example, the method steps are as follows. First, there is formed a first polysilicon layer overlying and in contact with the semiconductor substrate. Second, a plurality of conductive structures are patterned from the first polysilicon layer. Third, there is formed a dielectric layer having an upper planar surface and having a lower surface contacting the semiconductor substrate and the plurality of conductive structures from the first polysilicon layer. Fourth, there is formed a second polysilicon layer overlying and in contact with the dielectric layer. Fifth, a plurality of conductive structures are formed from the second polysilicon layer. Lastly, there is formed a metallic layer over the plurality of conductive structures from the second polysilicon layer.

Abstract: An apparatus and method for underfilling a silicon chip (16) to a substrate (12) by depositing an underfill dam (18) on the surface (20) of the substrate (12) prior to addition of the underfill material (14), is disclosed. A bead of underfill material (14) is provided on the substrate (12) about the periphery of the silicon chip (16), within the underfill dam (18). The underfill material (14) fills the gap (22) between the electrical contacts, the substrate (12) and the silicon chip (16) by capillary action and differential pressure created by a vacuum system (40).

Abstract: The present invention relates to a memory cell including two sets each including first and second transistors connected between high and low potentials, the first transistor being a P-channel transistor and the second one an N-channel transistor. Both sets include a third and a fourth N-channel transistor. The third transistor is connected between the high potential and the control electrode of the second transistor. The fourth transistor is connected between the low potential and the control electrode of the second transistor. The drains of the first and second transistors of each set form storage nodes. The sources and drains of the third and fourth transistors form input/output nodes, distinct from the storage nodes.

Abstract: A low noise preamplifier design which is configured such that the current through the first stage load resistor may be made relatively small in value making it possible to achieve a relatively large gain in the first stage thereby reducing the noise contribution of the load resistor and, concurrently, significantly reducing the noise contribution of the second stage as well. This is effectuated by supplying a substantially fixed amount of current to certain nodes in the first stage of the preamplifier through a pair of current sources, the currents being of an amount sufficient to subtract out the bias current that is applied through a series connected variable resistance, such as that of a magnetoresistive ("MR") read head. As a consequence, only a relatively small amount of current is actually fed through the load resistor, and its value may be increased to provide an increased gain for the first stage.

Abstract: An integrated circuit preferably includes a plurality of enhancement-mode MOSFETs on a substrate with each MOSFET having an initial threshold voltage, and a plurality of resistors connected to define a resistor voltage divider for passively biasing the MOSFETs to produce an absolute value of an effective threshold voltage of each MOSFET to be lower than an absolute value of the initial threshold voltage. Accordingly, the effective threshold voltages may set to below a predetermined value, and lower supply voltages thereby readily accommodated. For integrated circuits having all n-channel MOSFETs, the threshold voltages are positive, and the voltage divider can be set accordingly. The invention is advantageously also used in CMOS integrated circuits having both p-channel and n-channel MOSFETs. The resistor voltage divider may preferably be set or trimmed after forming the MOSFETs.

Abstract: A driver circuit for a power device of a power driving stage is capable of providing slew rate control. The driver circuit includes the following elements: a charging source of current, a discharging source of current, a first switch, a second switch, a conductive device, a capacitive element, an amplifier, and the power device. Both the first and second switches receive a control signal. The elements of the driver circuit are configured such that the conductive device will conduct only when the following two conditions are met: the control signal is a certain logic level and the voltage generated by the amplifier is larger than a reference voltage. When the control signal transitions from a first to a second logic state, a charging current is delivered to the capacitive element, an output voltage of the driver circuit increased to the reference voltage, and a voltage on a control terminal of the power device also increases to a charge pump voltage level.

Abstract: A linear type of voltage regulator, having an input terminal adapted to receive a supply voltage thereon, and an output terminal adapted to deliver a regulated output voltage, includes a power transistor and a driving circuit therefor. The driving circuit includes an operational amplifier having a differential input stage biased by a bias current which varies proportionally with the output current of the regulator.

Abstract: The entire data path of a synchronous integrated circuit device is initialized in a test mode upon power-up of the synchronous integrated circuit device. Upon power-up of the integrated circuit device in the test mode, a clock signal (either an external clock signal or an associated internal clock signal) is internally clocked. As the clock signal goes to a low logic state upon power-up of the device, a master latch (flip-flop) element of the integrated circuit device is loaded with data and is allowed to conduct; a slave latch (flip-flop) element of the integrated circuit device does not conduct. As the clock signal goes to a high logic state, the data in the master latch is latched. Also upon the high logic state of the clock, the slave latch element is loaded with data and is allowed to conduct.

Abstract: A memory for storing a reorganizing array of an initial array of data of binary ones and zeros to enable decoding of the reorganized array to reproduce the information content of the initial array, and the method of reorganizing the initial array. The memory includes a data circuit array that has a plurality of memory cells arranged in rows and columns for storing the reorganized array. The memory also has a plurality of flag memory cells and a row of XOR gates and inverters. The initial array is divided into sections. Each row of each section of the initial array that has more ones than zeros is inverted, and the corresponding flag bit is also inverted. Each column of the initial array that has more ones than zeros is inverted, and the corresponding flag bit is also inverted. This is repeated until each row in each section and each column has at least as many ones as zeros, producing the reorganized array.

Abstract: A process for forming a structure of a high-frequency bipolar transistor on a layer of a semiconductor material with conductivity of a first type. The process includes forming a first shallow base region by implantation along a selected direction of implantation and using a dopant with a second type of conductivity. The region extends from a first surface of the semiconductor material layer and encloses, toward said first surface, an emitter region with conductivity of the first type. In accordance with the invention, the implantation step includes at least one process phase at which the direction of implantation is maintained at a predetermined angle significantly greatly than zero degrees from the direction of a normal line to said first surface. Preferably, the implantation angle is of about 45 degrees.

Abstract: A vertical structure, integrated bipolar transistor incorporating a current sensing resistor, comprises a collector region, a base region overlying the collector region, and an emitter region over the base region. The emitter region comprises a buried region a surface region, and a first vertical diffusion region connecting the buried layer to the surface region. A second vertical diffusion region connects the buried emitter layer periphery to a first surface contact, while the surface emitter region is contacted, along three peripheral sides thereof, by a second surface contact. The transistor current flows from the substrate, through the base to the buried emitter region. It is then conveyed into the vertical region, which represents a resistive path, and on reaching the surface region splits between two resistive paths included between the vertical region and the surface contacts.

Abstract: A circuit for enhancing chrominance transitions in a received chrominance video signal comprises a linear-phase digital filter supplied with an input stream of discrete chromatic image elements. The filter also has a high-pass transfer characteristic in a region of the frequency spectrum corresponding to an upper limit of a transmitted chrominance signal bandwidth for enhancing high-frequency components of the received chrominance signal. The circuit additionally includes non-linear digital post-processing circuitry which accepts as input an output of the filter and the input stream of discrete chromatic image elements. The non-linear post-processing circuitry acts on the output of the filter to eliminate distortions introduced in the received chrominance signal by the filter. The post-processing circuitry then detects if the received chrominance signal contains a transition pattern corresponding to predetermined patterns.

Abstract: A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary numbers, and a combinatorial network provides the final sum of the partial products. The partial products that include at least one of the more significant bits of either of the operands are performed by logic gating circuits which can be enabled to complement the partial product. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values.

Abstract: The present invention relates to a current amplifier including a first MOS transistor with a drain defining a first terminal for controlling the amplifier with a current and a source connected to a first supply line. It also includes a second MOS transistor with a drain forming a terminal of current output of the amplifier and a source connected to the first supply line, and at least one first bipolar transistor having a base connected to the first control terminal, an emitter connected to a gate of the first MOS transistor and is, via a first biasing resistor, connected to the first supply line and having a collector of the first bipolar transistor being connected to a second supply line.

Abstract: A flash EEPROM memory cell comprises source and drain regions defining a channel region therebetween, a floating gate and a control gate. The source and drain regions are first and second doped semiconductor regions of a first conductivity type formed in a first active area region of a semiconductor material layer of a second conductivity type; the control gate comprises a third doped semiconductor region of the first conductivity type formed in a second active area region of the semiconductor material layer; and the floating gate comprises a polysilicon strip insulatively disposed over the channel region and insulatively extending over the third doped semiconductor region.

Abstract: An analog switch formed from a MOS transistor switch includes means for applying to the bulk terminal of the transistor switch the voltage of either one of the two main terminals of the transistor switch as a function of the relation between the voltages of said main terminals.