Abstract: A oxide-based direct-access resistive nonvolatile memory may include within the interconnect portion of the integrated circuit a memory plane including capacitive memory cells extending in orthogonal first and second directions and each including a first electrode, a dielectric region and a second electrode. The memory plane may include conductive pads of square or rectangular shape forming the first electrodes. The stack of the dielectric layer and the second conductive layer covers the pads in the first direction and forms, in the second direction, conductive bands extending over and between the pads. The second electrodes may be formed by zones of the second bands facing the pads.

Abstract: A low-dropout voltage regulation device includes a power stage having an output terminal coupled to a load circuit, the load circuit being operable in a plurality of operating modes. The load circuit is configured to receive a different respective output current when in each of the plurality of operating modes. An error amplifier has an output coupled to an input terminal of the power stage. A compensation circuit is coupled to the input terminal of the power stage and is operable in a plurality of selectable configurations that are respectively tailored to the plurality of operating modes. The plurality of selectable configurations are selectable in response to a control signal representative of a current operating mode of the load circuit.

Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.

Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.

Abstract: A bipolar junction transistor includes an extrinsic collector region buried in a semiconductor substrate under an intrinsic collector region. Carbon-containing passivating regions are provided to delimit the intrinsic collector region. An insulating layer on the intrinsic collector region includes an opening within which an extrinsic base region is provided. A semiconductor layer overlies the insulating layer, is in contact with the extrinsic base region, and includes an opening with insulated sidewalls. The collector region of the transistor is provided between the insulated sidewalls.

Abstract: A sensor management system includes a cloud-based sensor configuration system and an electronic device. The electronic device includes a sensor unit. The sensor unit includes configuration data that controls operation of the sensor unit. The configuration data includes a classifier that classifies feature sets generated from sensor signals of the sensor unit. The electronic device sends sensor data to the cloud-based sensor configuration system. The cloud-based sensor configuration system analyzes the sensor data and generates a new classifier customized for the sensor unit based on the sensor data. The cloud-based sensor configuration system sends the new classifier to the electronic device. The electronic device replaces the classifier in the sensor unit with the new classifier.

Abstract: A measurement of the rotation speed of an object is made using a time-of-flight sensor configured to detect a passing of one or more of elements of the object through a given position. The time-of-flight sensor is further mounted on a one-person vehicle configured to protect the one-person vehicle against collisions through the making a time-of-flight measurement of a relative speed between the one-person vehicle and an obstacle.

Abstract: A method of making a bipolar transistor includes forming a stack of a first, second, third and fourth insulating layers on a substrate. An opening is formed in the stack to reach the substrate. An epitaxial process forms the collector of the transistor on the substrate and selectively etches an annular opening in the third layer. The intrinsic part of the base is then formed by epitaxy on the collector, with the intrinsic part being separated from the third layer by the annular opening. The junction between the collector and the intrinsic part of the base is surrounded by the second layer. The emitter is formed on the intrinsic part and the third layer is removed. A selective deposition of a semiconductor layer on the second layer and in direct contact with the intrinsic part forms the extrinsic part of the base.

Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.

Abstract: An optical device is mounted to an electronic circuit having a main face with at least one light source. The optical device is made from a block which includes, for each light source, a corresponding opening that passes through the block. The opening includes a cylindrical part with a threading on an inside surface.

Abstract: A waveform generator includes a system control unit and signal channels controlled by the system control unit and configured to supply driving signals for driving a respective transducer of an array of transducers. Each signal channel includes a sequential access memory having rows, where each row contains an instruction word configured to generate a respective step of a waveform to be generated. A memory output of the sequential access memory is defined by an output row at a fixed location. The waveform to be generated is defined by a block of instruction words. Each signal channel also includes an internal control unit that is configured to sequentially move the content of the sequential access memory, based on the instruction word currently at the memory output, so that sequences of instruction words are provided at the output row.

Abstract: An electronic device includes a carrier wafer having a front side and a back side, with an electrical connection network configured to connect the front side to the back side. An electronic chip is mounted on the front side of the carrier wafer and electrically connected to front pads of the electrical connection network. A sheet of a thermally conductive graphite or a pyrolytic graphite is added to the back side of the carrier wafer. The sheet includes apertures which leave back pads of the electrical connection network uncovered.

Abstract: A voltage regulator and a phase change memory are disclosed. In an embodiment a phase-change memory includes an array of a plurality of phase-change memory cells, an address decoder configured for receiving an address signal and selecting a sub-area in the array of the plurality of memory cells, the selected sub-area having a given number of bits of a data signal and a writing circuit including a control circuit configured for receiving the data signal and determining, for each memory cell in the selected sub-area, whether a respective bit of the data signal indicates that the memory cell is to be changed from the amorphous state to the polycrystalline state and one or more driving circuits supplied via a regulated voltage and configured for applying the set current for the first interval to the memory cells that are to be changed from the amorphous state to the polycrystalline state.

Abstract: A method can be used for addressing a slave integrated circuit connected to a bus. The slave integrated circuit has a default address on the bus. The method includes receiving, at the slave integrated circuit, an addressing message conveyed on the bus. The addressing message contains a replacement address. The method also includes replacing the default address within the slave integrated circuit with the replacement address upon receiving the addressing message, restarting the slave integrated circuit, and upon the restarting, assigning the replacement address as a new default address.

Abstract: A vertical photodiode includes an active area. The contacting pads for the diode terminals are laterally shifted away from the active area so as to not be located above or below the active area. The active area is formed in a layer of semiconductor material by a lower portion of a germanium area that is intrinsic and an upper portion of the germanium area that is doped with a first conductivity type. The vertical photodiode is optically coupled to a waveguide formed in the layer of semiconductor material.

Abstract: A resistance trimming circuit has a resolution of N=X+Y bits. Included is a first circuit with M resistors, where M=2X?1, with each of the M resistors having a resistance of R*(2Y)*i, i being an index having a value ranging from 1 to 2X?1. M switches are associated with the M resistors. Each of the M resistors is coupled between a first node and its one of the M switches, and each of the M switches couples its one of the M resistors to a second node. Included is a second circuit with P resistors, where P=2Y?1, with each of the P resistors having a resistance of R*i. P switches are associated with the P resistors. Each of the P resistors is coupled between the second node and its one of the P switches, and each of the P switches selectively couples its one of the P resistors to a third node.

Abstract: A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.

Abstract: A photodetection circuit includes a single photon avalanche diode (SPAD), and an active quenching circuit coupling the SPAD to an intermediate node and having a variable RC constant. The variable RC constant provides a first RC constant during an idle state so that when the SPAD detects a photon, the SPAD avalanches to begin quenching to set a magnitude of a voltage at a terminal of the SPAD to a quench voltage, the quench voltage being greater than a threshold voltage; a second RC constant greater than the first RC constant during a hold off period during which the quenching occurs so as to maintain the voltage at the terminal of the SPAD at a magnitude that is above the threshold voltage during the hold off period; and a third RC constant less than the second RC constant but greater than the first RC constant during a recharge period during which the SPAD is recharged.

Abstract: A photodiode include a first substrate layer of a first dopant type and a second substrate layer of a second dopant type on top of the first substrate layer. Semiconductor walls are provided in a semiconductor substrate which includes the first and second substrate layers. The semiconductor walls include: two outer semiconductor walls and at least one inside semiconductor wall positioned between the two outer semiconductor walls. Each inside semiconductor wall is located between two semiconductor walls having longer length.

Abstract: A MEMS inclinometer includes a substrate, a first mobile mass and a sensing unit. The sensing unit includes a second mobile mass, a number of elastic elements, which are interposed between the second mobile mass and the substrate and are compliant in a direction parallel to a first axis, and a number of elastic structures, each of which is interposed between the first and second mobile masses and is compliant in a direction parallel to the first axis and to a second axis. The sensing unit further includes a fixed electrode that is fixed with respect to the substrate and a mobile electrode fixed with respect to the second mobile mass, which form a variable capacitor.