Abstract: A quad signal generator circuit generates four 2N?1 bit control signals in response to a sampling clock and a 2N?1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N?1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2N?1 bit control signals. Outputs of the 2N?1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2N?1 bit control signals such that all logic states of bits of the four 2N?1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N?1 bit thermometer coded signal.

Abstract: The present disclosure is directed to a semiconductor die with multiple contact pads electrically coupled to a single lead via a single wire, and methods for fabricating the same. In one or more embodiments, multiple contact pads are electrically coupled to each other by a plurality of conductive layers stacked on top of each other. The uppermost conductive layer is then electrically coupled to a single lead via a single wire.

Abstract: A method selects one or a plurality of sets of values characterizing an electric power of a power source capable of powering a device coupled to the power source via a connection interface. The selection is carried out according to values, characterizing the power supplied by the power source, measured at the connection interface.

Abstract: The disclosure concerns an electronic component manufacturing method including a first step of etching at least one first layer followed, with no exposure to oxygen, by a second step of passivating the first layer.

Abstract: A wireless-power-circuit is operable in transceiver-mode and Q-factor-measurement-mode, and includes a bridge coupled to a coil, and having an output coupled to a rectified-voltage node. An excitation circuit, when in Q-factor-measurement-mode, drives the coil with a pulsed signal. A protection circuit couples the coil to a first node when in Q-factor-measurement-mode and decouples the coil from the first node when in transceiver-mode. A Q-factor sensing circuit includes an amplifier having inputs coupled to the first node and a common mode voltage (Vcm), and generating an output signal having an output voltage. A comparator generates a comparison output indicating Vcm crossing of a voltage at the first terminal of the coil, a processing circuit generating an enable signal based upon the comparison output, and an analog-to-digital-converter, when enabled, digitizing the output voltage for use in calculating a Q-factor of the coil.

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.

Abstract: A circuit includes a switching circuit including a first switch and a second switch. A current sensing circuit is coupled to the switching circuit to sense a first current through the first switch and to generate a first sensed current signal based on the sensed first current, and configured to sense a second current through the second switch and to generate a second sensed current signal based on the sensed second current. An output circuit is coupled to the current sensing circuit and is configured to generate a failure signal based on the first sensed current signal and the second sensed current signal.

Abstract: A current mirror includes first and second transistors having current paths coupled to an input current line. The current paths for the first and second transistors are referenced to ground via respective first and second resistors having resistance values twice a first resistance value. The first transistor is diode connected. A third transistor has a current path coupled to an output current line and referenced to ground via a third resistor having a second resistance value equal to the first resistance value divided by a mirror factor. Control terminals of the first and third transistors are coupled together, and further coupled to a control terminal of the second transistor through a coupling resistor. A first capacitor is coupled between ground and the control terminal of the second transistor unit. A second capacitor is coupled between ground and the current path through the third transistor.

Abstract: A capacitive electro-optical modulator includes a silicon layer, a germanium or silicon-germanium strip overlying the silicon layer, and a silicon strip overlying the germanium or silicon-germanium strip. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator is laterally adjacent the germanium or silicon-germanium strip and the silicon strip and has an upper surface that is flush with an upper surface of the silicon strip. An insulating layer overlies the insulator and the silicon strip. A layer of III-V material overlies the insulating layer. The layer of III-V material is formed as a third strip arranged facing the silicon strip and separated therefrom by a portion of the insulating layer.

Abstract: An electronic device includes a base substrate having a mounting face. An electronic chip is fastened onto the mounting face of the base substrate. A transparent encapsulation structure is bonded onto the base substrate. The transparent encapsulation structure includes a housing with an internal cavity defining a chamber housing the electronic chip. The encapsulation structure has an external face that supports a light-filtering optical wafer located facing an optical element of the electronic chip. An opaque cover covers the transparent encapsulation structure and includes a local opening facing the light-filtering optical wafer.

Abstract: A multi-phase electric motor includes a stator winding. The multi-phase electric motor is controlled by regulating a current flowing in the multi-phase electric motor in response to an applied voltage. An overload condition of the multi-phase electric motor is detected by monitoring a thermal increase of the value of a stator resistance of the stator winding of the multi-phase electric motor during a steady state condition of said multi-phase electric motor in which the current flowing in the motor has constant phase, and the motor is operating at constant load with constant speed.

Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.

Abstract: A photodiode includes an active area formed by intrinsic germanium. The active area is located within a cavity formed in a silicon layer. The cavity is defined by opposed side walls which are angled relative to a direction perpendicular to a bottom surface of the silicon layer. The angled side walls support epitaxial growth of the intrinsic germanium with minimal lattice defects.

Abstract: A memory device includes a memory array powered between a virtual supply and virtual ground nodes. A dummy memory array is powered between first and second nodes. A virtual supply generation circuit generates a virtual supply voltage at the virtual supply node as a function of a first control voltage. A virtual ground generation circuit generates a virtual ground at the virtual ground node as a function of a second control voltage. A first control voltage generation circuit coupled between the first node and a power supply voltage generates the first control voltage as tracking retention noise margin (RNM) of the memory array, the first control voltage falling as the RNM decreases. A second control voltage generation circuit coupled between the second node and ground generates the second control voltage as tracking RNM of the memory array, the second control voltage rising as the RNM decreases.

Abstract: A radiofrequency-powered device such as a wireless passive sensor node, for instance, comprises a radiofrequency energy harvesting circuit configured to be coupled to an antenna to harvest radiofrequency energy captured by the antenna from a radiofrequency signal. The radiofrequency energy harvesting circuit is configured to be coupled to an energy storage component to store therein energy harvested via the radiofrequency energy harvesting circuit. The device comprises user circuitry configured to be supplied with energy harvested via the radiofrequency energy harvesting circuit and to operate in accordance with one of a plurality of configurations as a function of configuration data supplied thereto. A receiver circuit coupled to the radiofrequency energy harvesting circuit is configured to receive a configuration data signal modulating the radiofrequency signal and supply to the user circuitry configuration data extracted from the configuration data signal received.

Abstract: A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package.

Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.

Abstract: A charge recovery driver is for a pair of loads, and includes first and second output nodes coupled to a pair of loads. During an initial phase, the first output node is grounded and the second output node is tied to the supply voltage. During a first phase, the first output node is coupled to the first tank capacitor and the second output node is coupled to the second tank capacitor. During a second phase, the first and second output nodes are coupled to one another. During a third phase, the second output node is coupled to the first tank capacitor and the first output node is coupled to the second tank capacitor. During a fourth phase, the first output node is coupled to the supply voltage and the second output node is coupled to ground. The third, second, and first phases are then repeated in that order.

Abstract: A determination is made as to whether touch pressure data acquired from each of a plurality of touch pressure sensors is indicative of abnormal operation. If abnormal operation is indicated, the touch pressure data from each of the plurality of touch pressure sensors, except those touch pressure sensors having touch pressure data indicative of abnormal operation, is summed. Then, the sum is multiplied by a correction factor to produce a touch pressure output indicative of physical force applied to the plurality of touch pressure sensors.