Patents Assigned to STMicroelectronics
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Patent number: 12086008Abstract: A system includes a control unit configured to be electrically connected to an input of a memory via a communication interface. The control unit includes a first power supply sector configured to be powered when the control unit is in an operating mode and a second power supply sector configured to be powered when the control unit is in the operating mode and in a low consumption mode. In the first power supply sector, the control unit includes a first configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the operating mode. In the second power supply sector, the control unit includes a second configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the low consumption mode.Type: GrantFiled: September 12, 2022Date of Patent: September 10, 2024Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics Design and Application S.R.O.Inventors: Jerome Lacan, Remi Collette, Christophe Eva, Milan Komarek
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Patent number: 12085393Abstract: A user context and/or activity detection device envisages a pressure sensor, configured to provide a pressure signal; an electrostatic-charge-variation sensor, configured to provide a charge-variation signal indicative of a variation of electrostatic charge associated with the user; and a processing unit, which is coupled to the pressure sensor and to the electrostatic-charge-variation sensor so as to receive the pressure signal and the charge-variation signal and is configured to jointly process the pressure signal and charge-variation signal for detecting changes in level or altitude.Type: GrantFiled: March 10, 2021Date of Patent: September 10, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Enrico Rosario Alessi, Fabio Passaniti
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Patent number: 12087683Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.Type: GrantFiled: December 30, 2021Date of Patent: September 10, 2024Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: François Tailliet, Guilhem Bouton
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Patent number: 12087708Abstract: A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.Type: GrantFiled: October 21, 2021Date of Patent: September 10, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoit Froment
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Patent number: 12086568Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.Type: GrantFiled: April 14, 2023Date of Patent: September 10, 2024Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Rupesh Singh
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Patent number: 12086358Abstract: A touch status monitor method includes detecting a touch on a touch screen when operating in a low-power detect scan mode. The method further includes, in response to detecting the touch, switching from the low-power detect scan mode to a low-power active scan mode and labeling the current event as a touch down event. The method further includes, in response to labeling the current event as the touch down event, applying a lock to prevent updating a baseline when entering the low-power detect scan mode. And the method further includes, in response to detecting that the touch has left the touch screen, releasing the lock, labeling the current event as a touch up event, switching from the low-power active scan mode to the low-power detect scan mode, and updating the baseline.Type: GrantFiled: November 2, 2023Date of Patent: September 10, 2024Assignee: STMicroelectronics International N.V.Inventors: Qiang Ma, Yuan Yun Wang
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Patent number: 12088429Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.Type: GrantFiled: February 22, 2022Date of Patent: September 10, 2024Assignees: STMicroelectronics Design and Application S.R.O., STMicroelectronics Application GmbHInventors: Fred Rennig, Vaclav Dvorak
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Patent number: 12086094Abstract: The present disclosure relates to a method of communication via serial bus, comprising: the conveyance by the serial bus of a frame comprising at least two consecutive cycles of a dominant state followed by a recessive state, the recessive states and dominant states having durations comprised between 2 and 5 times the duration of a data bit conveyed by the serial bus, and preferably above 1.8 ?s; and the detection by one or more circuits coupled to the serial bus of at least a part of the frame for triggering the passage from a sleep state to a wake state of the one or more circuits.Type: GrantFiled: September 4, 2020Date of Patent: September 10, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventor: Arnaud Dehamel
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Publication number: 20240296899Abstract: A system includes a write-data register and a read-data register, each clocked by a clock signal, and a first-in-first-out (FIFO) buffer coupled between the write-data register and the read-data register, the FIFO buffer including latches configured to store data. The system further includes glue logic with first, second, and third logic circuits configured to generate an internal write enable signal, an internal read valid signal, and an internal read enable signal based on an operational mode of the system. The system is configured to be selectively switched between a normal operational mode, where the latches are accessed for reading and writing by a read enable signal and write enable signal based on a read address signal and a write address signal, and a transition testing mode, where the latches are tested using the internal write enable signal, the internal read enable signal, and the internal read valid signal.Type: ApplicationFiled: May 13, 2024Publication date: September 5, 2024Applicant: STMicroelectronics International N.V.Inventors: Venkata Narayanan SRINIVASAN, Balwinder Singh SONI, Avneep Kumar GOYAL
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Publication number: 20240297043Abstract: A process for manufacturing a power electronic device, envisages: forming a semiconductor body of silicon carbide, having a first electrical conductivity and a first doping value, and defining a front surface; forming a Current Spreading Layer, CSL, in a surface portion of said semiconductor body facing the front surface, having the first electrical conductivity and a second doping value, greater than the first doping value; forming elementary cells of the power electronic device in an active area of the semiconductor body at the front surface. The step of forming the current spreading layer envisages performing a channeled ion implantation, in a channeling condition, for implanting doping ions having the first electrical conductivity within the semiconductor body.Type: ApplicationFiled: February 21, 2024Publication date: September 5, 2024Applicant: STMicroelectronics International N.V.Inventors: Alfio GUARNERA, Cateno Marco CAMALLERI, Edoardo ZANETTI, Laura Letizia SCALIA, Mario Pietro BERTOLINI, Massimiliano CANTIANO, Massimo BOSCAGLIA, Mario Giuseppe SAGGIO
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Publication number: 20240297640Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.Type: ApplicationFiled: May 7, 2024Publication date: September 5, 2024Applicant: STMICROELECTRONICS S.r.l.Inventors: Domenico TRIPODI, Luca GIUSSANI, Simone Ludwig DALLA STELLA
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Publication number: 20240297249Abstract: Method of manufacturing an electronic device, comprising the steps of: arranging a semiconductor body of N-type, having a lattice structure with spatial symmetry, comprising an active area an edge region surrounding the active area; forming, in the edge region, an intentionally damaged region wherein the lattice structure has no spatial symmetry; forming an edge termination region of P-type at the damaged region, by random implant; forming a current spreading layer, CSL, in the edge region at and lateral to the damaged region, by channeled implant. The CSL has, at the damaged region, a minimum thickness and, laterally to the damaged region, a maximum thickness. The minimum thickness is lower than the thickness of the edge termination region.Type: ApplicationFiled: February 21, 2024Publication date: September 5, 2024Applicant: STMicroelectronics International N.V.Inventors: Alfio GUARNERA, Mario Giuseppe SAGGIO, Cateno Marco CAMALLERI, Edoardo ZANETTI
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Publication number: 20240295454Abstract: A pressure-sensor includes a substrate with a cavity therein and a membrane suspended over the cavity. The cavity is connected to external air pressure so a change in external air pressure causes out-of-plane movement of the membrane. A frame suspended over the membrane includes a segment connected to the membrane but disconnected from other frame portions. A projection extends from the frame. A first spring is connected to the projection, a second spring is connected to the segment, and an end portion connects the springs so out-of-plane movement of the membrane applies out-of-plane force to the second spring, which is transferred to the first spring by the end portion and translated to an in-plane force by the first spring and applied to the projection. This causes lateral sliding movement of the frame with respect to the substrate. A capacitive-sensor detects sliding movement of the frame with respect to the substrate.Type: ApplicationFiled: March 3, 2023Publication date: September 5, 2024Applicant: STMicroelectronics International N.V.Inventors: Lorenzo BALDO, Filippo DANIELE, Enri DUQI
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Publication number: 20240297044Abstract: A manufacturing process provides for: forming a semiconductor body of silicon carbide, having a front surface; performing a localized ion implantation to form implanted regions in implant portions in the semiconductor body. The step of performing a localized ion implantation provides for: forming damaged regions at the front surface, separated from each other by the implant portions in a direction parallel to the front surface; performing a channeled ion implantation, for implanting doping ions within the semiconductor body and forming the implanted regions at the implant portions of the semiconductor body. The channeled ion implantation is performed in a self-aligned manner with respect to the damaged regions, which represent damaged regions of the silicon-carbide crystallographic lattice such as to block a propagation of the channeled ion implantation along a vertical axis orthogonal to the front surface, in a depth direction of the semiconductor body.Type: ApplicationFiled: February 21, 2024Publication date: September 5, 2024Applicant: STMicroelectronics International N.V.Inventors: Cateno Marco CAMALLERI, Mario Giuseppe SAGGIO, Edoardo ZANETTI, Gabriele BELLOCCHI
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Publication number: 20240295604Abstract: An integrated circuit includes a sequential logic circuit and a circuit configured to change operation as a function of state output signals provided by state flip-flops of the sequential logic circuit. With a test mode signal asserted, a test circuit writes and reads the content of the state flip-flops in order to test the operation of the sequential logic circuit. A processing system includes at least one storage circuit interposed between the circuit and a respective state output signal. Each storage circuit receives the respective state output signal and provides a modified state signal to the circuit. When the test mode signal is de-asserted, the storage circuit provides the received state output signal in a transparent manner to the circuit and stores the received state output signal to a storage element. When the test mode signal is asserted, the storage circuit provides the stored state output signal to the circuit.Type: ApplicationFiled: February 28, 2024Publication date: September 5, 2024Applicant: STMicroelectronics International N.V.Inventors: Gianluca TORTORA, Mario BARONE
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Publication number: 20240297147Abstract: A hybrid QFN and QFP integrated circuit package includes a leadframe with first second die pads supporting first and second integrated circuits, respectively. The leadframe further includes QFN conductive pads QFP conductive leads. A package housing encapsulates the first and second die pads, the first and second integrated circuits mounted thereto, the QFN conductive pads, and proximal ends of the QFP conductive leads. Distal ends of the QFP conductive leads extend away from side edges of the package housing. Bottom surfaces of the QFN conductive pads are exposed at a bottom surface of the package housing. The QFN conductive pads are located between the first and second die pads.Type: ApplicationFiled: February 14, 2024Publication date: September 5, 2024Applicant: STMicroelectronics International N.V.Inventors: Shei Meng LOO, Edsel DE JESUS
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Publication number: 20240297240Abstract: A semiconductor substrate has a substrate trench extending from a front surface and including a lower part and an upper part. A first insulation layer lines the substrate trench, and a first conductive material is insulated from the semiconductor substrate by the first insulating layer to form a transistor field plate electrode. A gate trench in the first insulation layer defines an integral part of the first insulating layer surrounding the first conductive material in an upper part of the substrate trench. A second insulating layer lines the semiconductor substrate at the upper part of the substrate trench in the gate trench. A second conductive material fills the gate. The second conductive material forms a transistor gate electrode that is insulated from the semiconductor substrate by the second insulating layer and further insulated from the first conductive material by the integral part of the first insulating layer.Type: ApplicationFiled: January 31, 2024Publication date: September 5, 2024Applicant: STMicroelectronics International N.V.Inventors: Voon Cheng NGWAN, Churn Weng YIM, Vincenzo ENEA
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Patent number: 12081286Abstract: A reader is adapted to wirelessly exchanging information with a wireless apparatus. The reader includes a signal generator configured to generate a modulation signal. An emitter/receptor stage is configured to be driven by the modulation signal. A switched-mode power supply is configured to power the emitter/receptor stage. The switched-mode power supply includes a power switch controlled in function of the modulation signal.Type: GrantFiled: September 30, 2019Date of Patent: September 3, 2024Assignees: STMICROELECTRONICS RAZVOJ POLPREVODNIKOV D.O.O., STMICROELECTRONICS FRANCEInventors: Francois Agut, Severin Trochut, Vinko Kunc
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Patent number: 12080327Abstract: An embodiment method includes rectifying a back electromotive force of a spindle motor in a hard disk drive and energizing a voice coil motor in the hard disk drive using the rectified back electromotive force of the spindle motor via a voice coil motor power stage to retract a head of the hard disk drive to a park position. The head is retracted by moving the head towards the park position during a first retract phase and retaining the head in the park position during a second retract phase by applying a bias voltage to the voice coil motor power stage during a bias interval of the second retract phase. The method also includes producing a saturation signal indicative of onset of saturation in the voice coil motor power stage and controlling the bias voltage during the second retract phase.Type: GrantFiled: July 19, 2023Date of Patent: September 3, 2024Assignee: STMicroelectronics S.r.l.Inventors: Ezio Galbiati, Michele Boscolo Berto, Giuseppe Maiocchi, Maurizio Ricci
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Patent number: 12081204Abstract: A power switch device includes a first terminal intended to be connected to a source of a first supply potential, a second terminal configured to supply a second potential, and a third terminal intended to be connected to a second source of a third supply potential. The device includes a first PMOS transistor having a source connected to the second terminal and a drain connected to the third terminal, a second PMOS transistor having a source connected to the second terminal, and a third PMOS transistor having a source connected to the first terminal and a drain connected to the drain of the second transistor. A control circuit generates gate control signals to control operation of the first, second and third PMOS transistors dependent on the first, second, and third supply potentials.Type: GrantFiled: August 10, 2022Date of Patent: September 3, 2024Assignee: STMicroelectronics (Rousset) SASInventor: Laurent Lopez