Patents Assigned to STMicroelectronics
  • HEMT DEVICE HAVING IMPROVED ON-STATE PERFORMANCE AND MANUFACTURING PROCESS THEREOF
    Publication number: 20240304710
    Abstract: A HEMT transistor has a body having a top surface and a heterostructure, and a gate region having a semiconductor material and arranged on the top surface of the body. The gate region has a first lateral sidewall and a second lateral sidewall opposite to the first lateral sidewall. The HEMT device further has a sealing layer of non-conductive material that extends on and in contact with the first and the second lateral sidewalls of the gate region; and a passivation layer of non-conductive material that has a surface portion. The surface portion extends on the top surface of the body, laterally to the first lateral sidewall of the gate region. The sealing layer and the passivation layer have different geometrical parameters and/or are of different material.
    Type: Application
    Filed: February 29, 2024
    Publication date: September 12, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Cristina TRINGALI, Aurore CONSTANT, Maria Eloisa CASTAGNA, Ferdinando IUCOLANO
  • ASYNCHRONOUS STATE MACHINE FOR A SWITCHING CONVERTER
    Publication number: 20240303092
    Abstract: An asynchronous finite state machine has states coupled by transitions each implemented by a flip-flop. Each flip-flop supplies a bit of a state of arrival of the corresponding transition, and receives a bit of an initial state of this transition on its data input and a first signal dedicated to the flip-flop on its control input. A circuit supplies, for each transition, a second signal of request for the transition. Another circuit generates based on the second signals, at each request for a transition and in the absence of a pulse of the first signals, a pulse of the first signal dedicated to the flip-flop of this transition, and a pulse of the first signal dedicated to each flip-flop supplying a bit to the flip-flop of the transition.
    Type: Application
    Filed: March 6, 2024
    Publication date: September 12, 2024
    Applicant: STMicroelectronics International N.V.
    Inventor: David CHESNEAU
  • METHOD OF MANUFACTURING AN ELECTRONIC CHIP COMPRISING A MEMORY CIRCUIT
    Publication number: 20240306401
    Abstract: The present disclosure relates to a process that includes the simultaneous formation of a first transistor in and on a first region of a substrate, of a second transistor in and on a second region of the substrate, of a third transistor in and on a third region of the substrate and of a memory cell in and on a fourth region of the substrate. The method includes the following successive steps: forming a first gate stack on the first region, a second gate stack on the second region, a third gate stack on the third region and a fourth stack on line with the fourth region; simultaneously etching a part of the third gate stack and the fourth stack the first and the second gate stacks being protected with a first mask; and simultaneously etching the first and the second gate stacks, the third gate stack and the fourth region of the semiconductor substrate being protected with a second mask.
    Type: Application
    Filed: February 26, 2024
    Publication date: September 12, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Remy BERTHELON, Olivier WEBER
  • WIRELESS POWER TRANSMISSION BETWEEN A POWER TRANSMITTER AND AN APPLIANCE
    Publication number: 20240305145
    Abstract: A wireless power receiving appliance is configured to wirelessly receive power from a wireless power transmitter. The appliance includes: an NFC device electromagnetically coupled to another NFC device of the wireless power transmitter and a field strength indicator. The field strength indicator: receives from an NFC antenna of the NFC device a representative signal of the strength of the NFC field between the NFC device and the another NFC device, compares a value of the representative signal with at least one reference value, and emits a user signal depending on the comparison between the value of the representative signal and the at least one reference value. The user signal displays an indication of the position of the appliance with respect to the wireless power transmitter.
    Type: Application
    Filed: March 6, 2024
    Publication date: September 12, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Martin RAMPETSREITER, Rene WUTTE, Asmira HUSKIC, Martin DENDA
  • RESISTOR
    Publication number: 20240304731
    Abstract: An electronic device includes first and second diffused resistors in contact with each other to form a PN junction. The device is configured so that a potential difference between the first and second resistors is constant at any point of the PN junction. The PN junction is reverse-biased.
    Type: Application
    Filed: March 4, 2024
    Publication date: September 12, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Francois TAILLIET, Marc BATTISTA
  • READING METHOD FOR A MEMORY
    Publication number: 20240304224
    Abstract: The present disclosure relates to a method of reading a word in a memory device, wherein the word is comprised in a first set of words that can be read by the memory device, each word of the first set comprising at least one byte of data, each word being contained in memory cells, the method comprising a pre-charging step during which the first set and at least a second set of words are pre-charged, a first terminal of each cell of the first and second sets being floating during the pre-charging step.
    Type: Application
    Filed: February 21, 2024
    Publication date: September 12, 2024
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Christophe GONCALVES, Marc BATTISTA, Francois TAILLIET
  • HEMT DEVICE HAVING A REDUCED ON-RESISTANCE AND MANUFACTURING PROCESS THEREOF
    Publication number: 20240304711
    Abstract: A HEMT transistor is formed on a semiconductor body having a semiconductive heterostructure. A gate region of a semiconductor material, is arranged on the semiconductor body and has lateral sides. Sealing regions of non-conductive material extend on the lateral sides of the gate region; and a passivation layer of non-conductive material has surface portions extending on the semiconductor body, on both sides of the gate region and at a distance therefrom. The sealing regions and the passivation regions have different characteristic, such as are of different material or have different thicknesses.
    Type: Application
    Filed: March 1, 2024
    Publication date: September 12, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Cristina TRINGALI, Aurore CONSTANT, Maria Eloisa CASTAGNA, Ferdinando IUCOLANO
  • PULSE WIDTH MODULATION CIRCUIT
    Publication number: 20240305203
    Abstract: The present disclosure relates to a pulse width modulation circuit of a switched-mode power supply formed in and on a monolithic semiconductor substrate with a face coated with a gallium nitride layer, said circuit being adapted to control a power transistor of said switched-mode power supply.
    Type: Application
    Filed: February 29, 2024
    Publication date: September 12, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Lionel ESTEVE, Loic BOURGUINE
  • METHOD FOR CALIBRATING A SWITCHING CONVERTER
    Publication number: 20240305197
    Abstract: A buck switching converter is calibrated using a method which alternates between first and second calibration phases. During each first calibration phase: a time period of low-side switch on state is kept constant and, for each current pulse in an inductor, a sign of a value of the current at the end of the time period of on state of the low-side switch is determined. Modification of a time period of high-side switch on state is made based on the determined sign. During each second calibration phase: a time period of high-side switch on state is kept constant and, for each current pulse in the inductor, a value of the current at the end of the time period of on state of the high-side switch is compared with a target value. Modification of the time period of low-side switch on state is made based on the comparison.
    Type: Application
    Filed: March 6, 2024
    Publication date: September 12, 2024
    Applicant: STMicroelectronics International N.V.
    Inventor: David CHESNEAU
  • MEMORY DEVICE
    Publication number: 20240304237
    Abstract: The present disclosure relates to a memory device including a sense amplifier, wherein the amplifier comprises a first inverter, wherein an input and an output of the inverter are coupled to a first transistor configured to be switched on during a step of pre-charging of a memory cell.
    Type: Application
    Filed: February 21, 2024
    Publication date: September 12, 2024
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Christophe GONCALVES, Marc BATTISTA, Francois TAILLIET
  • HEMT DEVICE HAVING A REDUCED GATE LEAKAGE AND MANUFACTURING PROCESS THEREOF
    Publication number: 20240304713
    Abstract: An HEMT device is formed on a semiconductor body having a semiconductive heterostructure. A control region of a semiconductor material, is arranged on the semiconductor body and has a top surface and lateral sides. A control terminal, of conductive material, extends on and in contact with the top surface of the control region. A passivation layer of non-conductive material, extends on the semiconductor body, partially on the top surface of the control region and on the lateral sides of the control region, laterally and at a distance from the control terminal.
    Type: Application
    Filed: February 29, 2024
    Publication date: September 12, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Ferdinando IUCOLANO, Aurore CONSTANT, Cristina TRINGALI, Maria Eloisa CASTAGNA
  • EMBEDDED MECHANICAL STOPPER FOR THERMAL SENSOR DEVICE
    Publication number: 20240302219
    Abstract: Disclosed herein are thermal sensor devices including TMOS devices with a mass suspended over a cavity by springs extending between a frame and the mass. The thermal sensor devices include stoppers that limit upward and/or downward movement of the springs and therefore the mass. These stoppers are formed from sidewalls supporting a top cap over the frame, springs, and mass. The stoppers are constructed by using various overlapping metal layers during fabrication. Details of forming the stoppers using these overlapping metal layers are contained here.
    Type: Application
    Filed: March 10, 2023
    Publication date: September 12, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Federico VERCESI, Silvia NICOLI, Cinzia DE MARCO
  • Calibration method for phase-locked loops and related circuit
    Patent number: 12088310
    Abstract: A voltage-controlled oscillator in a phase-locked loop circuit is calibrated via a dichotomous search in a set of candidate frequency bands via a sequence of subsequent halving steps that produce reduced subsets of the set of candidate frequency bands. The reduced subsets have respective upper bound values and lower bound values, as well as central values. The central value of the subset resulting from the halving step of index i in the sequence is a function of the average of the upper bound value and the lower bound value of the subset resulting from the halving step of index i?1 in the sequence.
    Type: Grant
    Filed: March 29, 2023
    Date of Patent: September 10, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Davide Nicolo Fortunato, Antonino Calcagno, Marco Vinciguerra, Angelo Scuderi, Gaetano Cosentino
  • SPAD photodiode
    Patent number: 12087873
    Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: September 10, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Antonin Zimmer, Dominique Golanski, Raul Andres Bianchi
  • Overvoltage protection circuit for a PMOS based switch
    Patent number: 12088085
    Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: September 10, 2024
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMicroelectronics International N.V.
    Inventors: Manoj Kumar, Ravinder Kumar, Nicolas Demange
  • MEMS device having an improved stress distribution and manufacturing process thereof
    Patent number: 12084341
    Abstract: A MEMS device is formed by a body of semiconductor material which defines a support structure. A pass-through cavity in the body is surrounded by the support structure. A movable structure is suspended in the pass-through cavity. An elastic structure extends in the pass-through cavity between the support structure and the movable structure. The elastic structure has a first and second portions and is subject, in use, to mechanical stress. The MEMS device is further formed by a metal region, which extends on the first portion of the elastic structure, and by a buried cavity in the elastic structure. The buried cavity extends between the first and the second portions of the elastic structure.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: September 10, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nicolo' Boni, Lorenzo Vinciguerra, Roberto Carminati, Massimiliano Merli
  • Systems and methods to monitor leakage current
    Patent number: 12085601
    Abstract: A system to monitor a MOSFET, the system including a switching arrangement configured to switchably isolate a gate terminal of the MOSFET and a source terminal of the MOSFET from a gate-control voltage source and a test circuit configured to detect a change in a gate-to-source voltage of the MOSFET over a test period, the test period occurring while the gate terminal and the source terminal are isolated.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: September 10, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Romeo Letor, Veronica Puntorieri
  • Circuit and method for on-chip leakage detection and compensation for memories
    Patent number: 12087368
    Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: September 10, 2024
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Arpit Vijayvergia, Vikas Rana
  • Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
    Patent number: 12087356
    Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: September 10, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj Ayodhyawasi
  • Sigma-delta analog-to-digital converter circuit with data sharing for power saving
    Patent number: 12088326
    Abstract: A continuous time, sigma-delta analog-to-digital converter circuit includes a sigma-delta modulator circuit configured to receive an analog input signal. A single bit quantizer of the modulator generates a digital output signal at a sampling frequency. A data storage circuit stores bits of the digital output signal and digital-to-analog converter (DAC) elements are actuated in response to the stored bits to generate an analog feedback signal for comparison to the analog input signal. A filter circuit includes polyphase signal processing paths and a summation circuit configured to sum outputs from the polyphase signal processing paths to generate a converted output signal. A fan out circuit selectively applies the stored bits from the data storage circuit to inputs of the polyphase signal processing paths of the filter circuit.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: September 10, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Abhishek Jain