Abstract: In accordance with an embodiment, a method includes: producing a set of delayed replicas of a reference clock signal, wherein delayed replicas in the set of delayed replicas have respective signal edges delayed in time by a mutual time delay therebetween; producing a set of edge detecting signals comprising edge detecting signals indicative of respective distances of edges of delayed replicas in the set of delayed replicas from an edge of a clock signal having a clock period; selecting based on edge detecting signals in the set of edge detecting signals a delayed replica in the set of delayed replicas having a distance from the clock signal edge that is shorter than the distance from the clock signal edge of any other delayed replica in the set of delayed replicas.

Abstract: An electronic system includes a control circuit to provide a binary control signal alternating between a first binary state during first phases and a second binary state during second phases; a screen controlled by the control signal, the screen emitting light during each first phase, and to not emit any light during each second phase; a light sensor under the screen or along the edge of the screen, and providing a measurement signal representative of a quantity of light received by the sensor during a measurement phase or a plurality of consecutive measurement phases; and a synchronization device to synchronize each measurement phase with a second phase.

Abstract: Methods of operating an induction geyser include drawing current through a resonant tank via a transistor, generating a changing magnetic field around the resonant tank. Owing to the strategic placement of the resonant tank in proximity to a fluid tank, the changing magnetic field envelopes the fluid tank. In a first method, the voltage across the transistor's conduction terminals is monitored, and when this voltage surpasses a predefined threshold, indicating an overvoltage condition, a corrective action is initiated in which a gate driver pulls up a gate drive signal that drives the transistor. In a second method, the current flowing between the transistor's conduction terminals is monitored, and upon detecting an overcurrent condition where the current exceeds a set threshold the gate driver is activated to pull down the gate drive signal. Both methods aim to keep operation of the geyser within desired parameters.

Abstract: The present disclosure relates to a switched-mode Power Supply Buck Converter comprising: a switch connected between a node receiving a supply potential and an internal node; another switch connected between the internal node and a node receiving a reference potential; an inductive element coupling the internal node to an output node; and a control circuit controlling the switches so that current pulses in the inductive element have a maximum value selected from among at least a first value and a second value based on an average current drawn at the output node.

Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.

Abstract: A system includes at least one first application and a shared software platform. The shared software platform identifies each first application a first random number. The first random number is stored in encrypted fashion in an executable code of the first application. The first application is further identified by a second number which is representative of the first random number. The second number is stored in a first portion of a memory only accessible to the shared software platform.

Abstract: Tray for containing electronic components formed by a bearing body, substantially planar, having a first and a second face. First holding structures extend from the first face of the bearing body and second holding structures extend from the second face of the bearing body. Each second holding structure is aligned with a respective first holding structure in a vertical direction perpendicular to the first and the second faces of the bearing body. Each first holding structure is formed by first protrusions mutually spaced by first spaces and arranged along a first closed line; each second holding structure is formed by second protrusions mutually spaced by second spaces and arranged along a second closed line. Each second protrusion is aligned, in parallel with the vertical direction, with the first spaces and each first protrusion is aligned, in parallel with the vertical direction, with the second spaces.

Abstract: A PMUT includes a substrate being doped and having a plurality of conductive vias formed therein, each conductive via formed of a portion of the substrate extending completely from a back side of the substrate to a front side of the substrate and being encircled by an isolating structure that electrically isolates that portion of the substrate from other portions of the substrate. An insulating layer stacked on the front side of the substrate and has through-holes therein over the plurality of conductive vias. An interconnection layer is stacked on the insulating layer and is connected to the plurality of conductive vias. A membrane carried is by the interconnection layer and underlying substrate, the membrane being shaped so as to delimit a chamber. A piezoelectric stack formed on the membrane over the chamber and vibrates the membrane in response to application of an alternating voltage to the piezoelectric stack.

Abstract: A buffer circuit for driving a GaN power switch includes an input node to receive an input signal and an output node to produce a gate signal for the GaN power switch. The buffer includes a push-pull stage that includes a first transistor coupled between a supply voltage node and the output node, a second transistor coupled between the supply voltage node and the output node, a third transistor coupled between the output node and a reference voltage node, and a fourth transistor coupled between the output node and the reference voltage node. The buffer includes a pre-buffer stage configured to receive the input signal and to produce respective driving signals for the first, second, third and fourth transistors to produce the gate signal at the output node in four consecutive phases.

Abstract: A system for performing scan testing on a device core uses a test access port (TAP). The TAP includes a test clock (TCK) pin, a test data in (TDI) pin, and a test mode select (TMS) pin, along with a test control register (TCR) associated with it. The TCR is used to set a scan mode signal, which configures the scan flip flops within the device core for scan testing and performs the scan testing on the device core. The TCR can also be reset to exit the scan testing, with the reset being triggered by a reset circuit receiving the deassertion of both a scan enable (SE) signal and a scan input (SI) signal during the capture-phase of scan testing.

Abstract: A wafer includes a semiconductor substrate, an interconnection network provided with metal layers and at least one ultra-low dielectric constant dielectric layer, at least one contact region and at least one dicing region. A hard mask is formed having a pattern that defines a dicing line. The formation of the hard mask includes a first etching of an opening in the dicing region to expose the semiconductor substrate in the dicing region, a second etching of an opening in the contact region to expose a surface of a metal contact in the contact region, and a chemical treatment for cleaning the uncovered surface of the metal contact. A vertical dielectric layer is deposited to cover edges of the opening defining the dicing line. This layer is deposited before the chemical treatment is performed.

Abstract: A system on chip (SoC) includes a CPU, a main bus, and a plurality of subsystems. The SoC also includes an address remapping module coupled between the CPU and the bus. The address remapping module quickly and efficiently changes any memory addresses that need to be changed with the CPU requests a read or write operation associated with the addresses.

Abstract: The present disclosure relates to a method of manufacturing first electronic components, each comprising a second electronic component, each second component comprising at least two contact metallizations, the method comprising: a) forming, on a substrate, at least two metal pillars; b) forming, over a portion of the surface of each pillar, a metallization of the component; c) covering the surface of the substrate, the pillars, and the metallizations of the first components with a first resin layer; d) removing the substrate to expose a surface of the pillars, opposite to the metallizations of the components; e) bonding and electrically connecting the second components, by their metallizations, to the surface of the pillars opposite to the metallizations of the first components; and f) expose the surface of the metallizations of the first components opposite to the pillars.

Abstract: The present description concerns a method of checking a first data element, executed by an electronic device comprising a processor and a memory, wherein said first data element is not stored in said memory and is divided in N second data elements independent from the first data element, each second data element being stored in said memory, and a result of an application of a XOR function to the N second elements being equal to the first data element, wherein an image of the first data element by a CRC function linear with respect to the XOR function is stored in said memory, and said method comprising a step, executed by said processor, of checking if said image of the first data element by said CRC function is equal to an application of the XOR function to the images of N second elements by said CRC function.

Abstract: The present description concerns a method of checking a first data element, executed by an electronic device comprising a processor and a memory, wherein the first data element is divided in N second data elements being stored in the memory, and first data element being equal to the sum, modulo the dimension of a space comprising the first data element, of the N second data elements, wherein an image of the first data element by a LCG function is stored in the memory, and the method comprising a step of checking if the image of the first data element by the LCG function is equal to the sum, modulo the module of the LCG function, of a product of an integer varying from 0 to N?1 and an image of the dimension by the LCG function, and of the images of the second data elements by the LCG function.

Abstract: An integrated circuit chip is bonded to a support. The chip includes a first connection pad and two second connection pads. The support includes a third connection pad and two fourth connection pads. A stack layers includes first, second, and third conductive layers and insulating layers. The first, second, and third conductive layers are separated from one another by the insulating layers. The second conductive layer is positioned between the first and third conductive layers. The first and third conductive layers electrically connect the two second connection pads to the two fourth connection pads. The second conductive layer electrically connects the first connection pad to the third connection pad.

Abstract: A voltage converter includes a circuit formed by a parallel association, connected between first and second nodes, of a first branch and a second branch. The first branch includes a first controlled rectifying element having a first impedance. The second branch includes a resistor associated in series with a second rectifying element having a second impedance substantially equal to the first impedance. The second rectifying element may, for example, be a triac having its gate coupled to receive a signal from an intermediate node in the series association of the second branch. Alternatively, the second rectifying element may be a thyristor having its gate coupled to receive a signal at the anode of the thyristor.

Abstract: A cell includes a Z2-FET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate.

Abstract: A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.

Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.