Abstract: Provided are techniques for protecting a transaction in near-field communication. Provided is an electronic device including a processor hosting an application, a near-field communication module, and a secure element distinct from the processor. The near-field communication module is configured to identify the type of terminal emitting a polling frame, addressed to the application, that the communication module receives by analyzing the type of the polling frame. The device is configured to compare the result of the analysis with at least one command received from the terminal during the implementation of an NFC transaction.

Abstract: A system includes a host processor, a memory, a hardware accelerator and a configuration controller. The host processor, in operation, controls execution of a multi-stage processing task. The memory, in operation, stores data and configuration information. The hardware accelerator, in operation preforms operations associated with stages of the multi-stage processing task. The configuration controller is coupled to the host processor, the hardware accelerator, and the memory. The configuration controller executes a linked list of configuration operations, for example, under control of a finite state machine. The linked list consists of configuration operations selected from a defined set of configuration operations. Executing the linked list of configuration operations configures the plurality of configuration registers of the hardware accelerator to control operations of the hardware accelerator associated with a stage of the multi-stage processing task.

Abstract: A photosensitive device includes a peripheral circuit semiconductor region, a photosensitive circuit semiconductor region including at least one group of at least two photosensitive elements configured to generate a photoelectric signal on a node called critical node. The device further includes an integrator circuit per group of photosensitive elements, each including: a differential circuit for each photosensitive element of the group, in the photosensitive circuit semiconductor region, an amplification circuit, in the peripheral circuit semiconductor region, and a feedback circuit for each photosensitive element of the group, comprising a capacitive element located in the photosensitive circuit semiconductor region coupled between the output node of the amplification circuit and the respective critical node.

Abstract: The present disclosure relates to a near-field communication device including a near-field communication controller. The near-field communication controller includes at least one first demodulator, adapted to apply a first type of demodulation to a first signal modulated according to a first or a second type of modulation; and at least one second demodulator, adapted to apply a second type of demodulation to the first signal.

Abstract: A microfluidic device for continuous ejection of fluids includes: a semiconductor body that laterally delimits chambers; an intermediate structure which forms membranes each delimiting a top of a corresponding chamber; and a nozzle body which overlies the intermediate structure. The device includes, for each chamber: a corresponding piezoelectric actuator; a supply channel which traverses the intermediate structure and communicates with the chamber; and a nozzle which traverses the nozzle body and communicates with the supply channel. Each actuator is configured to operate i) in a resting condition such that the pressure of a fluid within the corresponding chamber causes the fluid to pass through the supply channel and become ejected from the nozzle as a continuous stream, and ii) in an active condition, where it causes a deformation of the corresponding membrane and a consequent variation of the pressure of the fluid, causing a temporary interruption of the continuous stream.

Abstract: A LED driver chip includes driver circuits, each being coupled to a different pin and including a fault-detection circuit. Each fault-detection circuit includes a force circuit forcing current to a force node, and a sense circuit including a current sensor coupled to the force node, and a comparator comparing a voltage at the force node to a reference voltage to generate a comparison output. Control circuitry, in a pin-to-pin short detection mode, activates the force circuit of a first of the driver circuits and activates the sense circuit of a second of the driver circuits, in a pin-to-ground short detection mode, activates the force and the sense circuit of the same driver circuits. The comparison output of the comparator of the activated sense circuit, if is higher or if lower of the reference voltage, indicates if short between pin or to ground, respectively, is present.

Abstract: A method may include generating, within a device, separate and discrete wavelengths, and generating light intensity profiles based on an interaction between the separate and discrete wavelengths and a multi-wavelength diffractive optic element. The method may include detecting an object from light reflected from the object using the light intensity profiles. The light intensity profiles may include a shorter range light intensity profile and a longer range light intensity profile, each light intensity profile having different energy per solid angle patterns.

Abstract: An integrated device includes: a first die; a second die coupled in a stacked way on the first die along a vertical axis; a coupling region arranged between facing surfaces of the first die and of the second die, which face one another along the vertical axis and lie in a horizontal plane orthogonal to the vertical axis, for mechanical coupling of the first and second dies; electrical-contact elements carried by the facing surfaces of the first and second dies, aligned in pairs along the vertical axis; and conductive regions arranged between the pairs of electrical-contact elements carried by the facing surfaces of the first and second dies, for their electrical coupling. Supporting elements are arranged at the facing surface of at least one of the first and second dies and elastically support respective electrical-contact elements.

Abstract: An embodiment circuit comprises first and second output nodes with an inductor arranged therebetween, and first and second switches coupled to opposing ends of the inductor. The switches are switchable between non-conductive and conductive states to control current flow through the inductor and produce first and second output voltages. The current intensity through the inductor is compared with at least one reference value. Switching control circuitry is coupled with the first and second switches, the first and second output nodes, and current sensing circuitry, which is configured to control the switching frequency of the first and second switches as a function of the output voltages and a comparison at the current sensing circuitry. The switching control circuitry is configured to apply FLL-FFWD processing to produce the reference values as a function of a timing signal, targeting maintaining a constant target value for the converter switching frequency.

Abstract: An ambient temperature sensor is provided that may be coupled to a PCB. The ambient temperature sensor includes a package including a first cap and an insulating structure. The insulating structure is formed of thermally insulating material, and the first cap and the insulating structure delimit a first cavity. A semiconductor device is included and generates an electrical signal indicative of a temperature. The semiconductor device is fixed on top of the insulating structure and arranged within the first cavity. The package may be coupled to the PCB so that the insulating structure is interposed between the semiconductor device and the PCB. The insulating structure delimits a second cavity, which extends below the semiconductor device and is open laterally.

Abstract: A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius.

Abstract: An electronic circuit includes a plurality of transistors including: at least one first MOS transistor of a first conductivity type arranged inside and on top of at least one first active area of a semiconductor substrate and at least one second MOS transistor of the second conductivity type arranged inside and on top of at least one second active area of the semiconductor substrate. Each first active area is delimited by a first insulating region which is recessed with respect to a first surface of the semiconductor substrate by a first depth. Each second active area is delimited by a second insulating region which is flush with the first surface of the semiconductor substrate, or which is recessed with respect to the first surface of the semiconductor substrate by a second depth smaller than the first depth.

Abstract: A SOC includes a core, peripherals, and a bus for interconnecting the core and peripherals. Some peripherals can be selectively enabled or disabled on-demand. The SoC further includes peripheral enabling/disabling electronics and peripheral enabling/disabling circuitry coupled to the peripherals. The peripheral enabling/disabling electronics are directly connected to the peripheral enabling/disabling circuitry and are configured to store information items related to an enabled/disabled peripheral configuration, indicate the peripherals that are enabled and the peripherals that are disabled according to the enabled/disabled peripheral configuration, and provide the peripheral enabling/disabling circuitry with signals based on the stored information items. The peripheral enabling/disabling circuitry allows operation of the enabled peripherals and prevents operation of the disabled peripherals based on the signals received from the peripheral enabling/disabling electronics.

Abstract: A word line activation unit of an in-memory computation generates activation signals as a function of an input value. The in-memory computation device includes a memory array with a plurality of memory cells (each storing a computational weight) coupled to a bit line and each to a word line and a digital detector. A cell current flows through each memory cell as a function of the activation signal and the computational weight and a bit line current is generated as a function of a summation of the cell currents. The digital detector performs successive iterations on the bit line current. In each iteration: an integration stage generates an integration signal indicative of a time integral of the bit line current, and resets the integration signal when the integration signal reaches a threshold; and the counter stage updates the output signal in response to the integration signal reaching the threshold.

Abstract: A differential comparator circuit includes a voltage amplifier of negative gain receiving an analog input signal and generating an inverted analog input signal. The analog input signal and the inverted analog input signal form differential analog input signals. A comparator input circuit includes a first capacitive divider to generate a first signal as an average of the analog input signal and a first ramp signal, and a second capacitive divider to generate a second signal as an average of the inverted analog input signal and a second ramp signal, with the first and second ramp signals being differential ramp signals. The comparator is configured to compare the first and second signals to generate a signal transition having a timing based on the input signal.

Abstract: An electronic device includes a processor and one or more secure elements. The processor executes a first high-level operating system and a first application. The one or more secure elements execute a first low-level operating system to verify a reliability, an authenticity, or a reliability and an authenticity of the first high-level operating system, and execute a second low-level operating system to execute a second application and to perform wireless communication with the first application. At each booting of the electronic device, the first low-level operating system performs a verification of the reliability, of the authenticity, or of the reliability and the authenticity of the first high-level operating system. In response to a request from the first application to the second application, the second low-level operating system requests a result of the verification from the first low-level operating system, and transmits the result to the second application.

Abstract: An electronic device is configured to support at least two configurations, one of the configurations being installed. The device includes a memory. In a limited-access region of the memory, a binary word is stored. That binary word has: a first value representative of the version of the installed configuration; and at least one second value indicating which configurations can be installed. A method of configuration of the electronic device includes determining, according to the second value, whether the configuration which attempts to be installed is permitted.

Abstract: An electronic device includes a secure element and an application programming interface. The secure element, in operation, executes a first application. The application programming interface, in operation, verifies a reliability of a received command directed to the first application, and transmits the command and a result of the verification to the first application.

Abstract: An electronic circuit includes a transistor cell with multiple transistors arranged inside and on top of a semiconductor substrate. Each transistor has an active area. First insulating regions are at least partially located around the transistors and extend down to a first depth in the semiconductor substrate. Second insulating regions are positioned to insulate the active areas the transistors from one another. The second insulating regions extend down to a second depth in the semiconductor substrate, the second depth being greater than the first depth.

Abstract: An in-memory computation device includes a word line activation circuit that receives an input signal indicative of input values and provides activation signals each as a function of the input value. The in-memory computation device further includes a memory array, a biasing circuit generating a bias voltage and a digital detector. The memory array has memory cells coupled to a bit line and each to a word line. Each memory cell stores a computational weight. In response to an activation signal, a cell current flows through each memory cell as a function of the bias voltage, the activation signal and the computational weight. A bit line current flows through the bit line as a function of a summation of the cell currents. The digital detector is coupled to the bit line, samples the bit line current and, in response, provides an output signal.