Abstract: A method of driving a stepper motor in a feed-forward voltage mode may include for a desired speed for the stepper motor setting an amplitude of a sinusoidal phase voltage of the stepper motor to be equal to a sum of an expected back-electromotive force (BEMF) amplitude estimated as a function of the desired speed, and a product of a desired phase current amplitude and an estimated absolute value of an impedance of the stepper motor.

Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.

Abstract: A circuit for converting a measured variable capacitance to an output voltage signal includes a charge amplifier circuit selectively coupled to an integrator circuit. The charge amplifier circuit, in one implementation, is configured as a high pass filter. In another implementation, the charge amplifier circuit is configured as a combination high pass and low pass filter. The charge amplifier circuit is selectively coupled to the integrator circuit when the circuit forces a switch in voltage across a measurement capacitor.

Abstract: A protocol for collision avoidance in inter and intra basic service set broadcast/multicast communication in a wireless network is disclosed. An access point reserves a broadcast transmission time and conveys that reservation to each of its associated stations. Using a beacon or an action frame, the transmission reservation time is sent to all stations and other neighboring access points within range of the primary access point. Upon receiving the broadcast transmission time reservation, each station associated with the reserving access point and any neighboring access points set their network allocation vector thus preventing frame transmission or reception during the now reserved transmission time.

Abstract: Apparatus for transmitting a clock and data from a first module to a second module connected by a single outward line and a single return line, comprising: means for transmitting a data pulse on the single outward line comprising means for asserting a first edge on said single outward line, said first edge representing a timing edge for the clock and means for asserting a second edge on the single outward line a selectable time period after said first edge, said selectable time period representing said data; and means for receiving a return pulse on said single return path comprising means for receiving a first edge and a second edge on the single return line, the first and second edges being separated by a first time period, said first time period representing an acknowledgement.

Abstract: A method for producing a deep trench in a substrate includes a series of elementary etch cycles each etching a portion of the trench. Each elementary cycle includes deposition of a passivation layer on the sidewalls and the bottom of the trench portion etched during previous cycles; followed by pulsed plasma anisotropic ion etching of the trench portion etched during previous cycles, the etching; being implemented in an atmosphere comprising a passivating species; and including a first etch sequence followed by a second etch sequence of less power than the power of the first etch sequence. The first etch sequence etches the passivation layer deposited in the bottom of the portion so as to access the substrate and etches the free substrate at the bottom of the portion while leaving a passivation layer on sidewalls of the portion.

Abstract: A passive bond pad condition sense structure may be configured to be electrically stimulated and tested for detecting an anomalous or altered electrical characteristic caused by stress or aging of the bond pad capacitively coupled to it. The related bond pad condition testing or monitoring system may include relatively simple stimulating and sensing circuits that may be wholly embedded in the integrated circuit device.

Abstract: A vertical bidirectional switch of the type having its control referenced to the rear surface, including on its rear surface a first main electrode and on its front surface a second main electrode and a gate electrode, this switch being controllable by a positive voltage between its gate and its first electrode, wherein the gate electrode is arranged on the front surface of a via crossing the chip in which the switch is formed.

Abstract: An insulating region for a semiconductor wafer and a method of forming same. The insulating region can include a tri-layer structure of silicon oxide, boron nitride and silicon oxide. The insulating region may be used to insulate a semiconductor device layer from an underlying bulk semiconductor substrate. The insulating region can be formed by coating the sides of a very thin cavity with silicon oxide, and filling the remainder of the cavity between the silicon oxide regions with boron nitride.

Abstract: A thin film amorphous silicon solar cell may have front contact between a hydrogenated amorphous silicon layer and a transparent conductive oxide layer. The cell may include a layer of a refractory metal, chosen among the group composed of molybdenum, tungsten, tantalum and titanium, of thickness adapted to ensure a light transmittance of at least 80%, interposed therebetween, before growing by PECVD a hydrogenated amorphous silicon p-i-n light absorption layer over it. A refractory metal layer of just about 1 nm thickness may effectively shield the oxide from the reactive plasma, thereby preventing a diffused defect when forming the p.i.n. layer that would favor recombination of light-generated charge carriers.

Abstract: A method for electrically programming a non-volatile memory in which a programming cycle includes prior addressing of memory cells from an initial address corresponding to a first row and a column of a memory plane. The method may include addressing the memory cells in a second consecutive row when the end of the first row i is reached to store data on bits with consecutive and increasing addresses in two consecutive rows.

Abstract: A wireless system including a plurality of WRAN's operating on different channels identifies and addresses a number of important issues relating to the current CBP mechanism (in D0.3) used for inter-cell discovery and communication. The present invention provides fundamental remedies to respectively resolve these issues. Moreover, an Enhanced Coexistence Beaconing Protocol (CBP) is provided that allows efficient, scalable, and backward-compatible cross-channel inter-cell communications for IEEE 802.22 systems.

Abstract: A voltage regulator for a regulated voltage generator configured to generate an operating voltage and including a variable comparison voltage generator, a comparison voltage, a partition branch including a plurality of active devices of a resistive type to receive the operating voltage and supply an intermediate voltage correlated to the operating voltage, and a comparator, to receive the comparison voltage and the intermediate voltage and supply a regulation signal for the regulated-voltage generator.

Abstract: A bidirectional power transistor formed horizontally in a semiconductor layer disposed on a heavily-doped semiconductor wafer with an interposed insulating layer, the wafer being capable of being biased to a reference voltage, the product of the average dopant concentration and of the thickness of the semiconductor layer ranging between 5·1011 cm?2 and 5·1012 cm?2.

Abstract: The invention relates to a method for organizing the registers of a peripheral in memory, the peripheral including at least one control register to be addressed in memory to store configuration data of the peripheral, one transmission register to be addressed in memory to store data to be transmitted from the memory to the peripheral, and one reception register to be addressed in memory to store data to be transmitted from the peripheral to the memory, the method including: duplicating, within a data memory range, the transmission/reception register to different contiguous addresses; and implementing in memory the control registers at contiguous addresses at the level of a memory range adjacent to the memory range where the transmission/reception register has been duplicated.

Abstract: Systems and methods for achieving multiple supply voltage compatibility of an input/output (I/O) ring of an integrated circuit (IC) chip. The IC chip includes a core surrounded by the I/O ring which includes a voltage detector circuit. An I/O supply voltage of the IC chip is sensed by the voltage detector circuit to generate a control signal. The control signal is used to configure the I/O ring to operate at the I/O supply voltage of the I/O ring, thus enabling the IC to operate at multiple supply voltage levels.

Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same are disclosed. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self-testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self-test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

Abstract: A distributed multiband coupling circuit including: a number n of first and of second terminals equal to the number of frequency bands; a third terminal and a fourth terminal; a number n of distributed couplers equal to the number of frequency bands, all couplers being identical and sized according to the highest frequency band, and each coupler including a first conductive line between first and second ports intended to convey a signal to be transmitted in the concerned frequency band, and a second conductive line coupled to the first one between third and fourth ports; a first set of resistive splitters in cascade between the third ports of the couplers, a terminal of the splitter associated with the first coupler being connected to the third terminal of the coupling circuit; and a second set of resistive splitters in cascade between the fourth ports of the couplers, a terminal of the splitter associated with the first coupler being connected to the fourth terminal of the coupling circuit.

Abstract: A method distributes personalized circuits to one or more parties. The method distributes a generic circuit to each party, encrypts a unique personalization value using a secret encryption key, and transmits each encrypted personalization value to the corresponding party. Each party then stores the encrypted personalization value in their circuit. The stored encrypted personalization value allows a piece of software to be properly executed by the circuit. A semiconductor integrated circuit is arranged to execute a piece of software that inputs a personalization value as an input parameter. The circuit comprises a personalization memory arranged to store an encrypted personalization value; a key memory for storing a decryption key; a control unit comprising a cryptographic circuit arranged to decrypt the encrypted personalization value using the decryption key; and a processor arranged to receive the decrypted personalization value and execute the software using the decrypted personalization value.

Abstract: A system and method of locating the position of a satellite or a user using a satellite positioning system. The system and method includes receiving, at a terminal, satellite positioning data for at least one specified time period over a communications channel. In addition, the system includes storing, at the terminal, the satellite positioning data for the at least one specified time period. Responsive to an event at a later time, the system generally calculates, at the terminal, the satellite position at the later time based only on the satellite positioning data for the at least one specified time period.